PRAM Reset Pulse Generation Based on Set Pulse Timing

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Solution Overview

Problem

Conventional phase-change random-access memory (PRAM) devices cannot simultaneously program set data and reset data to different memory cells, and during read-while-write operations, noise on the write path can damage read data, leading to errors.

Innovation Solution

A method and device that generate a set pulse and a reset pulse based on a programmed delay, allowing simultaneous programming of data to non-volatile memory cells using separate switching circuits, with the reset pulse generated in response to the set pulse and adjusted for optimal timing to minimize noise and errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional PRAM performs read operation during write operation (RWW), then operational efficiency is improved, but noise on write path damages read data causing errors

Engineering Contradiction:
Improveoperational efficiencyVSAvoiddata accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the write operation into distinct phases by controlling the timing and duration of write pulses to different memory cells. By using separate pulse generation circuits for different memory cells and controlling their activation times, the system allows RWW operations while minimizing interference between write and read paths through temporal segmentation of write operations.

Inventive Principle:
Principle #1Segmentation

2Productivity

If simultaneous programming of set data and reset data to different memory cells is implemented, then productivity is improved, but device complexity increases

Engineering Contradiction:
Improveprogramming speedVSAvoidcircuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the memory array into multiple independently controllable memory cells, each with its own switching circuit. This segmentation allows simultaneous programming of different data (set and reset) to different memory cells using separate write pulses, thereby achieving parallel operation and improved productivity without requiring a complete redesign of the memory architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamically controllable switching circuits that can be independently activated and deactivated based on the programming requirements. The switching circuits respond to control signals that determine when each memory cell receives write pulses, enabling flexible simultaneous programming operations while managing circuit complexity through dynamic control rather than static hardwired connections.

Inventive Principle:
Principle #15Dynamics

3Manufacturing precision

If write pulse duration is extended to ensure complete programming, then manufacturing precision is improved, but read-while-write noise increases

Engineering Contradiction:
Improveprogramming completenessVSAvoidwrite noise
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent implements preliminary action by generating and applying write pulses with precisely controlled durations that are optimized to complete programming before extended periods. By carefully calculating and setting the pulse width to be sufficient for reliable programming but not excessively long, the system achieves complete programming while limiting the duration of noise generation, thus reducing interference with concurrent read operations.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables simultaneous programming of data to multiple memory cells while reducing read-while-write noise, improving operational efficiency and accuracy by synchronizing the activation and deactivation of pulses.

Implementation Method 1

The phase-change material changes from a crystalline state (low electrical resistance) to an amorphous state (high electrical resistance) and vice versa due to Joule heating caused by current or voltage supplied to the phase-change material

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Data Source

PatentUS8787100B2Non-volatile memory device generating a reset pulse based on a set pulse, and method of operating the same
Publication Date: 2014.07.22 SAMSUNG ELECTRONICS CO LTD
  • US8787100B2 patent drawing
  • US8787100B2 patent drawing
  • US8787100B2 patent drawing

AI summary

A non-volatile memory device includes a set pulse generator configured to generate a set pulse, a reset pulse generator configured to generate a reset pulse based on the set pulse, and a write driver block configured to write second data to a second non-volatile memory cell using the reset pulse, while writing first data to a first non-volatile memory cell using the set pulse.