Multi-bit PRAM Storage Node Using Segmented Phase Change Layers
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Solution Overview
Problem
Conventional phase change random-access memory (PRAM) devices face challenges in reducing transistor size due to decreased current supply capability, limiting integration density and restricted to writing only 2-bit data, as they require a phase change current that is difficult to achieve with smaller transistors.
Innovation Solution
A resistive memory device with a storage node configuration that includes multiple phase change layers separated by barrier layers, allowing for reduced current requirements and enabling the writing of at least 2-bit data by utilizing chalcogenide or transition metal oxide materials and metal or insulating barrier layers for efficient electron tunneling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the transistor size is reduced to improve integration density, then the integration density is improved, but the current supply capability deteriorates
Solution Approach 1:
The storage node is divided into multiple phase change layers (first phase change layer, second phase change layer, and third phase change layer), each contributing to the overall resistance change. This segmentation allows the total resistance modulation to be distributed across multiple smaller components, reducing the current burden on each individual layer and enabling operation with smaller transistors that have limited current supply capability.
Solution Approach 2:
Multiple phase change layers are stacked in series between the lower and upper electrodes, creating a nested structure where each layer contributes to the resistance modulation. The barrier layers are positioned between the phase change layers, forming a nested configuration that optimizes the electrical characteristics while maintaining a compact vertical structure suitable for high integration density.
2Reliability
If a phase change current is applied to change the GST layer to amorphous state to write data, then data writing is achieved, but the current requirement exceeds the capability of smaller transistors
Solution Approach 1:
The data writing function is segmented across multiple phase change layers, each requiring a smaller current to induce phase change. The cumulative resistance change from multiple layers achieves the necessary signal modulation without requiring any single layer to handle the full current burden, thereby enabling reliable data writing with lower current from smaller transistors.
Solution Approach 2:
The invention changes the electrical parameters of the storage node by introducing multiple phase change layers with different resistance characteristics. This parameter change allows the storage node to achieve sufficient resistance modulation for reliable data writing while operating at lower current levels that are compatible with scaled-down transistor capabilities.
3Quantity of substance
If multiple phase change layers are used to enable multi-bit data writing, then the data storage capacity is improved, but the device complexity increases
Solution Approach 1:
The storage node is segmented into multiple phase change layers, where each layer can independently contribute to the resistance state, enabling multi-bit data storage. This segmentation increases data storage capacity while the systematic arrangement of layers with barrier layers in between maintains a manageable structural complexity through repeated modular units.
Solution Approach 2:
Each phase change layer serves multiple functions: it contributes to resistance modulation for data storage, provides thermal isolation when separated by barrier layers, and can be independently controlled for multi-bit encoding. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity despite the enhanced data storage capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for high integration density and low driving voltage operation, enabling the writing of multiple data bits using currents lower than the maximum allowable for the transistor, thus overcoming the limitations of conventional PRAM devices.
Implementation Method 1
A storage node in a PRAM includes a phase change layer that changes between an amorphous and a crystalline phase according to a given condition. The phase change layer exhibits high resistance in the amorphous state and low resistance in the crystalline state.
Implementation Method 2
utilizing chalcogenide or transition metal oxide materials and metal or insulating barrier layers for efficient electron tunneling
Data Source
AI summary
Provided are a multi-bit memory device having resistive material layers as a storage node, and methods of manufacturing and operating the same. The memory device includes a substrate, a transistor formed on the substrate, and a storage node coupled to the transistor, wherein the storage node includes: a lower electrode connected to the substrate; a first phase change layer formed on the lower electrode; a first barrier layer overlying the first phase change layer; a second phase change layer overlying the first barrier layer; and an upper electrode formed on the second phase change layer.