PRBS Generator Expansion for Fast Memory Data Strobes
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Solution Overview
Problem
Existing memory device controllers struggle to generate pseudorandom binary sequences (PRBS) at a frequency matching faster data strobe signals, leading to inefficiencies in operations like built-in self-test (BIST), as they typically output one bit per clock cycle while needing multiple bits synchronously.
Innovation Solution
A PRBS generator that outputs multiple bits corresponding to multiple clock cycles, including the current and subsequent cycles, based on the frequency of the data strobe signal, allowing for synchronization with faster data strobe frequencies, such as 16 times the clock signal frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a PRBS generator outputs one bit per clock cycle, then the device complexity is low, but the productivity is insufficient for faster data strobe signals
Solution Approach 1:
The PRBS generation function is segmented into two independent parts: a slow clocked LFSR that generates intermediate bits at low frequency, and a combinatorial logic unit that expands these intermediate bits into multiple PRBS bits per clock cycle. This segmentation allows the complex high-speed generation task to be divided into manageable low-speed generation plus fast combinatorial expansion.
Solution Approach 2:
The LFSR performs preliminary action by pre-generating intermediate PRBS bits at a slower, manageable clock frequency. These intermediate bits are then expanded combinatorially to produce the final high-frequency PRBS output, effectively performing the heavy generation work beforehand at a lower speed requirement.
2Adaptability or versatility
If the PRBS generator operates at the same frequency as the clock signal, then the reliability is maintained, but the adaptability to faster data strobe signals deteriorates
Solution Approach 1:
Intermediate PRBS bits serve as a mediator between the slow clock domain and the fast data strobe domain. The LFSR generates these intermediate bits reliably at the clock frequency, and the combinatorial logic transforms them into the high-frequency output needed for fast data strobe signals, bridging the frequency gap while maintaining reliability.
Solution Approach 2:
The system changes the parameter of PRBS output frequency dynamically by adjusting how many bits are generated per clock cycle based on the data strobe frequency requirement. The same LFSR can support different output frequencies by changing the expansion factor in the combinatorial logic, providing adaptability without sacrificing the reliability of the base generation process.
Data Source
AI summary
Methods, systems, and devices related to generating, by a pseudorandom binary sequence (PRBS) generator of a memory module, a PRBS comprising a first plurality of bits corresponding to a plurality of cycles of a clock signal of the memory module subsequent to a current cycle of the clock signal. Generation of the PRBS can be based on an intermediate PRBS comprising a second plurality of bits corresponding to the current cycle of the clock signal. During each respective cycle of the clock signal, a respective subset of the PRBS can be communicated from the PRBS generator to a memory device of the memory module. Each respective subset of the PRBS comprises a quantity of bits based on a frequency of a data strobe signal of the memory device relative to a frequency of the clock signal.