PRBS Generator for 2.5D IC Lane Error Identification
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Solution Overview
Problem
Memory and logic testing of 2.5D ICs is costly and inefficient, often locating general problem areas rather than specific error locations due to the large area requirements and external equipment needed for signal generation.
Innovation Solution
The implementation of a pseudo-random binary sequence (PRBS) generator and checker in a 2.5-dimensional integrated circuit, which outputs test signals on parallel lanes and compares them with reference signals to identify specific lanes associated with errors, reducing area overhead and testing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional testing methods are used for 2.5D ICs, then general problem areas can be located, but specific error locations cannot be identified and testing is costly and inefficient
Solution Approach 1:
The patent segments the testing process by assigning dedicated PRBS generators and checkers to specific dies within the 2.5D IC package. Each die can independently generate and verify test signals on its connected lanes, allowing parallel testing of multiple lanes simultaneously. This segmentation enables precise identification of which specific lane has errors while maintaining high testing throughput through parallel operation.
2Ease of operation
If external equipment is used for signal generation, then testing can be performed, but area overhead and device complexity increase
Solution Approach 1:
The patent merges the test signal generation and verification functions directly into the 2.5D IC package by integrating PRBS generators and checkers within the dies. This consolidation eliminates the need for external testing equipment, reducing area overhead and simplifying the testing operation. The testing functionality becomes an inherent part of the packaged device rather than requiring separate external systems.
Solution Approach 2:
The 2.5D IC package performs self-testing through integrated PRBS generators that create test signals and checkers that verify signal integrity on each lane. The system is largely self-sufficient, requiring minimal external equipment beyond basic signal capture. Each die can autonomously generate test patterns and identify errors on its connected interposer lanes without external intervention.
3Reliability
If large area is allocated for testing, then comprehensive coverage is achieved, but chip area available for functional circuits is reduced
Solution Approach 1:
The patent implements partial testing by allowing each die to selectively test specific lanes connected to it on the interposer. Rather than requiring all dies to test all lanes simultaneously, the system performs targeted testing on relevant connections. This partial action approach achieves sufficient testing coverage for reliability while minimizing the area overhead dedicated to testing circuits.
Data Source
AI summary
A device includes a first die including a pseudo-random binary sequence (“PRBS”) generator that outputs test signals on parallel lanes. The device further includes a second die comprising a PRBS checker that compares at least a portion of the test signals with reference signals to identify a particular lane associated with an error.