PRBS Generator Using Segmented Lanes for High-Speed Testing

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Solution Overview

Problem

Existing pseudo-random binary sequence (PRBS) generators for high-speed integrated circuits face challenges in power consumption and area requirements due to extensive multiplexing, making it difficult to implement full-rate PRBS generators at high speeds for chip-to-chip communication testing.

Innovation Solution

A pseudo-random binary sequence generator architecture with four lanes, each comprising a latch group connected in series and operating at half clock frequency, using XOR logic gates to double the data rate, reducing the number of building blocks and power consumption while maintaining maximum length sequence behavior.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If extensive multiplexing is used to double the data rate in PRBS generators, then the data rate is improved, but power consumption increases considerably

Engineering Contradiction:

Improvedata rateVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The PRBS generator is divided into multiple independent lanes (e.g., 4 lanes), each generating a portion of the output sequence. This segmentation allows the system to achieve high data rates through parallel operation of multiple low-frequency lanes rather than using extensive multiplexing in a single high-frequency lane, thereby reducing power consumption while maintaining high overall data rate.

Inventive Principle:

Principle #1Segmentation

2Speed

If extensive multiplexing is used to double the data rate in PRBS generators, then the data rate is improved, but the area requirements increase

Engineering Contradiction:

Improvedata rateVSAvoidarea

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The generator is segmented into multiple lanes that operate in parallel at lower frequencies. This approach reduces the area required compared to a single high-frequency lane with extensive multiplexing, as each lane uses fewer multiplexing resources and the overall architecture is more area-efficient.

Inventive Principle:

Principle #1Segmentation

3Speed

If full-rate PRBS generators are implemented at high speeds, then the data rate is improved, but the number of building blocks and power consumption increase

Engineering Contradiction:

Improvedata rateVSAvoidnumber of building blocks

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The high-speed PRBS generator is implemented by segmenting the functionality across multiple lanes operating at lower frequencies. This reduces the complexity of individual building blocks within each lane compared to a single high-speed lane, as each lane requires fewer high-speed multiplexers and retiming circuits.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11774496B2Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof

Publication Date: 2023.10.03 INDIAN INSTITUTE OF TECHNOLOGY

AI summary

Disclosed herein is a pseudo-random binary sequence (PRBS) generator (200) for performing on-chip testing. It comprises of a plurality of lanes (L1-L4), wherein each lane comprises a latch group (Lg1-Lg4) capable of receiving clock signals, wherein a number of latches in each latch group is based on an output sequence to be generated for performing the on-chip testing. Each latch group is having at least one of a flip-flop and a latch is further connected with a plurality of logic gates in such a manner that an output, generated by the at least one of the flip-flop and the latch of each latch group, is provided as an input to the plurality of logic gates.