Serial Link Initialization Using PRBS for Interconnect Adaptation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current interconnect architectures in high-performance computing systems face challenges in efficiently managing communication between multiple processors and devices, leading to bottlenecks in data transfer and power consumption, especially as the number of processing units increases.
Innovation Solution
A High Performance Interconnect (HPI) architecture is introduced, featuring a layered protocol stack with a transaction layer, link layer, and physical layer, along with power management and fault handling mechanisms, to enable efficient data transfer and power optimization across multiple processor sockets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect, then device complexity is reduced, but communication speed and data transfer efficiency deteriorate
Solution Approach 1:
The patent segments the interconnect architecture into multiple point-to-point links instead of using a single multi-drop bus. Each processor socket is connected to the interconnect fabric through dedicated serial links, allowing simultaneous independent communications between multiple pairs of devices, thereby increasing overall communication speed without requiring complex arbitration logic.
Solution Approach 2:
The patent replaces traditional electrical parallel bus architecture with serial point-to-point interconnects using differential signaling. This substitution enables higher communication speeds by using serialized data transmission with embedded clocking, eliminating the need for complex parallel signal synchronization while achieving superior performance.
2Power
If the number of processing units is increased, then computing power is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic link training and power management states where interconnect links can be dynamically activated or deactivated based on communication demands. When processors are idle or communication is minimal, links can enter low-power states, reducing overall power consumption while maintaining the capability to scale computing power when needed.
3Power
If the number of processing units is increased, then computing power is improved, but communication bottlenecks worsen
Solution Approach 1:
The patent segments the communication fabric into multiple independent point-to-point serial links rather than relying on a shared parallel bus. This segmentation allows multiple simultaneous communications to occur in parallel across different link pairs, eliminating communication bottlenecks that would arise from increased processor density on traditional architectures.
4Adaptability or versatility
If full blown interconnect architectures are used, then communication capability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal point-to-point interconnect fabric that can handle multiple types of communications (memory accesses, I/O operations, processor-to-processor communication) through the same physical infrastructure. The layered protocol stack provides multi-functionality at the protocol level while the physical layer remains relatively simple, achieving high adaptability without proportionally increasing device complexity.
Data Source
AI summary
A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.