PrDFE Selection Circuitry With Hold State for Faster Signaling
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Solution Overview
Problem
High-speed electronic signaling in communication systems faces challenges due to timing delays in decision feedback equalization, particularly in partial response decision feedback equalizers, which hinder effective utilization of feedback data at increasing signaling rates, leading to difficulties in compensating for inter-symbol interference.
Innovation Solution
The implementation of a partial response decision feedback equalizer with selection circuitry that employs a hold state and multiplexer circuitry to reduce critical timing paths, allowing for faster signaling rates by selectively freezing outputs and avoiding the need for flip-flops or latches in the control loop, thus reducing delays and preventing race conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional feedback circuitry is used in partial response decision feedback equalizers, then the equalizer can operate at lower signaling rates, but timing delays prevent effective utilization of feedback data at higher signaling rates
Solution Approach 1:
The patent extracts and removes the problematic feedback path from the critical timing loop by using a tapped delay line to store feedback data outside the main decision loop. This allows the feedback data to be captured and stored without introducing timing delays that would prevent effective utilization at high signaling rates.
Solution Approach 2:
The patent introduces a tapped delay line as an intermediary element between the feedback data source and the decision logic. This intermediary stores the feedback data and makes it available when needed without creating timing conflicts, enabling the system to operate at higher signaling rates by mediating the data flow timing.
2Reliability
If flip-flops or latches are used in the control loop to maintain data state, then timing delays are introduced, but without them race conditions may occur
Solution Approach 1:
The patent removes flip-flops and latches from the critical decision loop, extracting the state-holding function to a tapped delay line structure. This eliminates the timing delays associated with flip-flop and latch operation while preventing race conditions through the alternative storage mechanism.
Solution Approach 2:
The patent creates multiple copies of the feedback data at different time points using the tapped delay line, allowing the system to access historical data values without requiring state-holding elements in the critical path. This copying approach replaces the need for flip-flops and latches while maintaining reliability.
3Speed
If the feedback path circuitry operates at high speeds to match increased signaling rates, then timing delays are reduced, but the circuitry becomes difficult to implement and control
Solution Approach 1:
The patent replaces the mechanical/electronic feedback path circuitry that would need to operate at high speeds with a tapped delay line structure. This substitution allows the feedback function to be implemented with simpler, slower circuitry that does not need to match the high signaling rates, reducing implementation difficulty while maintaining effectiveness.
Data Source
AI summary
A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.