Pre-biasing Circuit for Synchronous Buck Converter Switch Node
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Solution Overview
Problem
Synchronous buck converters face inefficiencies due to shoot-through current, noise, and undershoot issues, which reduce their performance and increase power loss, despite advancements like non-overlap topologies and fast drivers, which introduce peak currents and noise.
Innovation Solution
A voltage reducing circuit with a pre-biasing circuit that applies bias voltages to high-side and low-side transistors before switching, allowing quick transitions with minimal current, reducing noise and improving efficiency by managing the slew rate of the switch node voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If fast drivers are used to reduce dead time between transistor switching, then switching speed is improved, but peak currents increase introducing noise and reducing efficiency
Solution Approach 1:
The pre-biasing circuit applies bias voltages to the gate terminals of transistors before switching occurs, preparing them in advance for rapid transition. This preliminary action allows the transistors to switch quickly without requiring large peak currents from the driver, as the biasing has already positioned them near the switching threshold.
Solution Approach 2:
The circuit dynamically adjusts the bias voltages applied to transistor gates based on operating conditions such as load current and switching state. By changing these voltage parameters adaptively, the circuit optimizes switching speed while minimizing peak current requirements and associated noise across different operating scenarios.
2Reliability
If non-overlap topology is used to prevent shoot-through, then reliability is improved, but dead time increases causing power loss
Solution Approach 1:
The pre-biasing circuit begins adjusting transistor gate voltages before the actual switching event, so that by the time switching occurs, the transistors are already positioned to transition rapidly. This eliminates or minimizes the dead time between transistor state changes while maintaining reliable shoot-through prevention through controlled voltage transitions.
Solution Approach 2:
The circuit uses dynamic, adaptive biasing voltages that change based on real-time operating conditions rather than fixed time delays. This allows the system to maintain shoot-through protection while optimizing the timing and duration of transistor transitions to minimize power loss during switching.
3Device complexity
If body diode conduction is allowed during transitions, then simplicity is maintained, but noise and efficiency are degraded due to bulk diode and substrate currents
Solution Approach 1:
The pre-biasing circuit adjusts the gate-source voltage parameters of transistors to keep them above the body diode threshold voltage during switching transitions. By dynamically controlling these voltage parameters, the circuit prevents body diode conduction and associated harmful currents while maintaining the simple synchronous rectifier topology without additional components.
Data Source
AI summary
A voltage reducing circuit comprises a power switch circuit portion comprising a high-side and low-side field-effect-transistors connected at a switch node. The power switch circuit portion has an on-state wherein the high-side transistor is enabled and the low-side transistor is disabled and, vice versa, an off-state. An energy storage circuit portion comprising an inductor connected to the switch node is arranged to provide an output voltage. A drive circuit portion receives a pulse width modulation control signal and outputs pulse width modulated (PWM) drive signals. A pre-biasing circuit portion applies bias voltages to the gate terminals of the high-side and low-side transistors in response to the PWM drive signals, wherein the pre-biasing circuit portion is arranged such that the bias voltage applied to the gate terminal of the currently disabled transistor is set to an intermediate voltage before switching between the on-state and off-state.