Pre-charge Equalization Circuit for DRAM Bit Line Leakage

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Solution Overview

Problem

Random access memory devices, such as DRAM and PSRAM, experience bit line leakage currents due to periodic activation of pre-charge signals, leading to increased stand-by current and inefficiencies in data retention and refresh operations.

Innovation Solution

A pre-charge equalization circuit that periodically activates a pre-charge voltage to complementary bit lines during self-refresh or stand-by modes, and temporarily activates after refresh operations to eliminate leakage currents by ensuring bit lines are only pre-charged when necessary, thereby reducing floating states and leakage paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the pre-charge signal is continuously activated to maintain bit lines at high voltage for sense amplification, then data reading capability is improved, but bit line leakage current increases leading to higher stand-by power consumption

Engineering Contradiction:

Improvedata reading capabilityVSAvoidstand-by power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The pre-charge signal is activated periodically rather than continuously. During self-refresh mode, the pre-charge signal is activated only during the refresh operation window (tCBR) and deactivated during intervals, thereby maintaining bit line voltage only when necessary for refresh operations while reducing stand-by power consumption during periods when no read or refresh operations are performed.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The pre-charge signal activation state is dynamically adjusted based on operational mode. In self-refresh mode, activation occurs periodically during refresh windows. In active mode, activation occurs during read operations and address transition detection (ATD) pulses. This dynamic adjustment optimizes the balance between data retention and power consumption.

Inventive Principle:

Principle #15Dynamics

2Reliability

If the pre-charge signal is activated frequently to ensure data retention during self-refresh mode, then data retention reliability is improved, but bit line leakage current increases

Engineering Contradiction:

Improvedata retentionVSAvoidbit line leakage current

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The pre-charge signal is activated periodically at the refresh rate (typically every 64ms or 16ms) during self-refresh mode, rather than continuously. This periodic activation maintains data retention by refreshing charged capacitors at necessary intervals while allowing bit lines to discharge and reducing leakage current during intervals between refresh operations.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The harmful continuous pre-charge activation is extracted and removed, retaining only the necessary periodic activations during refresh operations. This separates the essential function (periodic refresh) from the harmful continuous state, thereby reducing bit line leakage current while maintaining data retention.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If the pre-charge signal is activated during every access operation to enable sense amplification, then read/write operation reliability is improved, but power consumption increases due to repeated pre-charge cycles

Engineering Contradiction:

Improveread/write operation reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The pre-charge signal is activated periodically during access operations based on address transition detection (ATD) pulses. Each ATD pulse triggers a pre-charge activation followed by refresh and pre-charge operations, ensuring sense amplification readiness only when address changes occur, thereby reducing unnecessary pre-charge cycles and associated power consumption.

Inventive Principle:

Principle #19Periodic action

4Use of energy by moving object

If the pre-charge signal activation period is shortened to reduce bit line leakage current, then power consumption is reduced, but data retention reliability deteriorates

Engineering Contradiction:

Improvepower consumptionVSAvoiddata retention reliability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The pre-charge signal activation parameters are optimized to match the specific retention characteristics of the memory device. The activation period and duration are adjusted based on capacitor charge leakage rates, ensuring that pre-charge operations occur at intervals sufficient to maintain data integrity while minimizing unnecessary activations that would increase power consumption.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8391092B2Circuit and method for eliminating bit line leakage current in random access memory devices

Publication Date: 2013.03.05 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC

AI summary

A method for eliminating bit line leakage current of a memory cell in random access memory devices comprises the steps of: periodically activating a pre-charge equalization circuit, which provides a pre-charge voltage to a pair of complementary bit lines of a memory cell, if the memory cell is in a self-refresh mode or a standby mode; and temporarily activating the pre-charge equalization circuit after the memory cell is refreshed if the memory cell is in the self-refresh mode or the standby mode.