Pre-decoder for Dual Power Memory with Level Shifting
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Solution Overview
Problem
In deep sub-micron process technologies, memory device reliability in system on chips (SOCs) is compromised due to low supply voltages and threshold voltage mismatch, leading to read/write failures and increased defect density, especially in SRAMs, where conventional dual power rail pre-decoders increase layout area and gate delay.
Innovation Solution
A pre-decoder design for dual power memory devices that includes a clock generator, address latch and decoder, level shifter, and processing unit, where signals are powered by different supply voltages to generate a pulse signal for dual power rail word line drivers, optimizing the timing path without increasing the clock period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a level shifter is disposed in the data transmission path for each word line driver, then voltage level conversion is achieved, but layout area and gate delay are increased
Solution Approach 1:
The patent merges the level shifting function into the word line driver structure itself, eliminating the need for separate level shifters in the data transmission path. The word line driver is designed to directly output signals at the appropriate voltage level (CVDD) for the memory array, combining the driving and voltage conversion functions in a single unit, thereby reducing layout area.
Solution Approach 2:
The patent extracts the level shifting function from the data transmission path and relocates it to the word line driver output stage. By taking out the level shifter from the critical data path and placing it where it no longer adds delay, the design eliminates the trade-off between voltage conversion and timing performance.
2Reliability
If a level shifter is disposed in the pulse signal transmission path, then voltage level conversion is achieved, but gate delay is increased
Solution Approach 1:
The level shifting function is merged into the word line driver output stage, which is already on the critical timing path. This allows the pulse signal to be generated at the correct voltage level without passing through an additional level shifter, thereby eliminating the extra gate delay that would otherwise be introduced by a separate level shifter in the transmission path.
3Loss of energy
If supply voltage is decreased to reduce power consumption, then energy efficiency is improved, but read/write failure occurs due to threshold voltage mismatch
Solution Approach 1:
The patent applies different supply voltages to different parts of the system: the random logic operates at the lower supply voltage VDD for energy efficiency, while the memory array operates at the higher supply voltage CVDD to ensure reliable read/write operations. This local quality approach allows each subsystem to operate at its optimal voltage level, balancing power consumption and reliability.
Data Source
AI summary
A pre-decoder for providing a pulse signal to a dual power rail word line driver is provided. The pre-decoder includes a clock generator, an address latch and decoder, a level shifter and a processing unit. The clock generator generates a first signal according to a clock, wherein the first signal is powered by a first supply voltage. The address latch and decoder decodes an address to obtain a second signal according to the first signal. The level shifter generates a third signal according to the first signal, wherein the third signal is powered by a second supply voltage higher than the first supply voltage. The processing unit generates the pulse signal according to the second signal and the third signal, wherein the pulse signal is powered by the second supply voltage.