Pre-emphasis Signal Generator for Variable Resistance Memory Write Speed

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Solution Overview

Problem

Variable resistance memory devices face challenges in efficiently programming memory cells due to increasing RC delay in internal wires, leading to longer set-up times and slower write speeds, especially as memory devices become more integrated.

Innovation Solution

A circuit and method that generate a write signal by combining a pre-emphasis signal with a program signal, where the pre-emphasis signal is adjusted based on the location of the to-be-programmed memory cell within the memory cell array, allowing for varying pulse widths and magnitudes to optimize write current delivery, thereby reducing RC delay and enhancing write speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory devices become more integrated, then device density increases, but RC delay in internal wires increases leading to slower write speeds

Engineering Contradiction:
Improvedevice densityVSAvoidwrite speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent applies local quality by generating different pre-emphasis signal strengths based on the location of memory cells within the array. Memory cells at different positions receive tailored pre-emphasis signals that account for their specific RC delay characteristics, with cells experiencing higher delay receiving stronger pre-emphasis. This location-dependent approach optimizes write speed for each region while maintaining high device density integration.

Inventive Principle:
Principle #3Local quality

2Device complexity

If uniform write signal is applied to all memory cells, then circuit complexity is reduced, but write speed varies due to position-dependent RC delay

Engineering Contradiction:
Improvecircuit complexityVSAvoidwrite speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent implements parameter changes by dynamically adjusting the pre-emphasis signal parameters (strength, duration) based on memory cell location. The system modifies signal characteristics rather than maintaining a fixed uniform signal, allowing optimization of write speed for different positions within the memory array while managing circuit complexity through systematic parameter variation.

Inventive Principle:
Principle #35Parameter changes

3Speed

If pre-emphasis signal is applied to all memory cells, then write speed improves, but unnecessary signal processing increases for cells with low RC delay

Engineering Contradiction:
Improvewrite speedVSAvoidset-up time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and preparing location-specific pre-emphasis signal parameters before the actual write operation. The system determines the appropriate pre-emphasis strength based on memory cell position in advance, allowing optimized signal delivery without unnecessary processing for cells that require minimal or no pre-emphasis, thereby reducing overall set-up time while improving write speed.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8837197B2Circuit for generating write signal, variable resistance memory device, and method for programming variable resistance memory
Publication Date: 2014.09.16 SAMSUNG ELECTRONICS CO LTD
  • US8837197B2 patent drawing
  • US8837197B2 patent drawing
  • US8837197B2 patent drawing

AI summary

A circuit for generating a write signal includes a pre-emphasis signal generator that receives location information of a to-be-programmed memory cell and generates a pre-emphasis signal depending on the location information of the to-be-programmed memory cell, and a write driver that generates a program signal corresponding to data to be programmed in the to-be-programmed memory cell. A write signal is generated by combining the program signal with the pre-emphasis signal supplied from the pre-emphasis signal generator, and the write signal output to the to-be-programmed memory cell.