Pre-Memory Phase Initialization Using eDRAM and Cache as RAM

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Solution Overview

Problem

The increasing size and complexity of BIOS code and firmware in modern computing devices exceed the capacity of processor cache memory used for temporary storage during boot operations, leading to a need for alternative temporary storage solutions before main system memory is initialized.

Innovation Solution

A computing device determines the availability of embedded dynamic random-access memory (eDRAM) and Peripheral Component Interconnect Express (PCIe) memory, using these for temporary storage of BIOS and firmware instructions if available, or initializing a portion of the cache memory as 'Cache as RAM' if neither is available, until main memory is initialized.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cache memory is used as temporary RAM for pre-memory phase initialization, then the boot process can proceed before main memory is available, but the total storage capacity is limited by the size of cache memory

Engineering Contradiction:
Improveboot process reliabilityVSAvoidtemporary storage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent transitions from using only cache memory (one-dimensional solution) to utilizing PCIe device memory as an additional storage dimension. This allows the system to overcome the capacity limitations of cache memory by accessing a separate memory resource through the PCIe interface, effectively adding another layer of temporary storage availability during pre-memory initialization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent makes PCIe device memory serve multiple functions: it can be used as temporary RAM for BIOS/firmware execution, as storage for boot images, and as an alternative when cache memory is insufficient. This multi-functional approach allows a single PCIe device to replace what would traditionally require multiple specialized components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If BIOS code and firmware size increase to provide more features, then device functionality improves, but the available cache memory becomes insufficient for temporary storage

Engineering Contradiction:
Improvedevice functionalityVSAvoidtemporary storage capacity
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent loads boot images and initializes PCIe device memory in advance, before the main BIOS execution phase. This preliminary preparation ensures that when the system needs temporary storage during boot, the PCIe memory is already configured and ready, eliminating the need to compress or truncate BIOS/firmware code due to cache memory limitations.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If cache memory is initialized as temporary RAM, then boot operations can be performed before main memory initialization, but the amount of temporarily storable data reaches capacity

Engineering Contradiction:
Improveboot operation speedVSAvoidtemporary storage capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent introduces PCIe device memory as an intermediary storage resource between the processor and main memory. During pre-memory initialization, this intermediary provides additional temporary storage capacity without interfering with the fast cache memory operations, allowing both cache and PCIe memory to work together in a hierarchical temporary storage system.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9563437B2Technologies for pre-memory phase initialization of a computing device
Publication Date: 2017.02.07 INTEL CORP
  • US9563437B2 patent drawing
  • US9563437B2 patent drawing
  • US9563437B2 patent drawing

AI summary

Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.