Pre-molding Chip Bonding for Semiconductor Alignment and Stress Reduction
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Solution Overview
Problem
Existing semiconductor device bonding processes result in inconsistent application of bonding layers and undesirable stresses on electrical contacts, particularly in multi-chip devices with fine distribution circuitry, due to alignment discrepancies and material properties.
Innovation Solution
A pre-molding chip bonding method where electrical contacts are pressed into a bonding layer before curing, allowing for precise alignment and reduced stress, using a combination of a molding layer, bonding layer, and buildup layer for mechanical stability, with the bonding layer being cured under controlled conditions to minimize warpage and enhance positioning accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bonding layer is applied by flowing between electrical contacts, then the bonding layer can be applied to secure chips, but inconsistent application and undesirable stresses occur on electrical contacts
Solution Approach 1:
The bonding layer is applied to the carrier before the chips are mounted, allowing the bonding layer to be cured and stabilized in position before the chips are pressed into it. This preliminary application eliminates the inconsistency and stress problems that occur when bonding layer is applied after chip placement.
2Adaptability or versatility
If fine distribution circuitry is used with multi-chip devices, then device functionality is improved, but alignment discrepancies cause unreliable connections
Solution Approach 1:
The bonding layer acts as an intermediary between the chips and the carrier, providing a compliant material that accommodates alignment discrepancies. When chips are pressed into the cured bonding layer, the bonding layer deforms to ensure proper alignment and connection, enabling reliable fine-pitch distribution circuitry even with 15 micrometer alignment tolerance.
3Measurement precision
If chips are pressed into bonding layer before curing, then positioning accuracy is improved, but warpage may occur during curing
Solution Approach 1:
The curing process parameters (temperature, time, pressure) are carefully controlled and optimized to minimize warpage while maintaining the positioning accuracy achieved during pressing. The bonding layer composition is also adjusted to reduce differential thermal expansion and shrinkage during curing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures consistent bonding layer application, reduces stress on electrical contacts, and improves alignment accuracy, leading to more reliable and stable semiconductor devices with reduced warpage and increased positioning precision.
Implementation Method 1
curing the bonding layer, wherein the bonding layer, as cured, is coupled, at least in part, to the electrical contact
Data Source
AI summary
This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact.