Pre-Silicon Testing Critical Path Noise Simulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated circuit design testing methods, such as IR STA, are inadequate as they assume simultaneous worst-case voltage drop across all nodes, do not model adaptive clock generators, and fail to consider transient noise levels and ground bounce effects, leading to pessimistic design assumptions and increased power consumption and die size.
Innovation Solution
A computer-implemented method for pre-silicon testing that identifies critical paths, performs noise simulations to generate voltage waveforms, applies these waveforms to netlists, and conducts timing analyses to determine slack times, allowing for more accurate modeling of temporal, spatial, and adaptive clock effects, thereby focusing design efforts on critical paths that limit maximum operating frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If IR STA is performed to determine timing impact of worst case voltage drop, then timing analysis is completed, but pessimistic design assumptions lead to increased power consumption and die area
Solution Approach 1:
The patent applies local quality by performing timing analysis on specific critical paths rather than all circuit paths. The system identifies and analyzes only those paths that are actually sensitive to voltage drop, rather than uniformly analyzing the entire circuit. This selective approach maintains timing analysis accuracy for critical paths while reducing overall computational power consumption.
Solution Approach 2:
The patent segments the timing analysis process into distinct phases: first performing a coarse analysis to identify critical paths, then performing detailed timing analysis only on those identified critical paths. This segmentation allows the system to avoid unnecessary analysis of non-critical paths, reducing power consumption while maintaining accuracy for the paths that matter most.
2Device complexity
If IR STA assumes simultaneous worst case voltage drop at all nodes, then timing analysis is simplified, but design margins become excessive and overdesign occurs
Solution Approach 1:
The patent applies preliminary action by first performing a voltage drop analysis to identify which nodes actually experience worst-case voltage drop, before performing the detailed timing analysis. This preliminary identification step allows the subsequent timing analysis to focus only on affected nodes with realistic voltage conditions, rather than assuming all nodes experience worst-case conditions simultaneously. The result is more accurate design margins without excessive complexity.
3Device complexity
If IR STA models only supply voltage noise, then analysis is simplified, but ground bounce effects are not captured
Solution Approach 1:
The patent merges the modeling of supply voltage noise and ground bounce effects into a unified timing analysis framework. Rather than treating them as separate analyses, the system combines both noise sources and evaluates their combined impact on critical paths. This integrated approach maintains manageable modeling complexity while significantly improving noise modeling accuracy and reliability.
4Reliability
If designers increase power grid size to reduce IR drop, then resistance and voltage drop are reduced, but metal area for signal routing decreases and die size increases
Solution Approach 1:
The patent applies parameter changes by using detailed critical path identification to enable more accurate voltage drop parameters in timing analysis. Instead of using conservative worst-case parameters that would require oversized power grids, the system uses actual measured or simulated voltage drop values on critical paths. This allows the power grid to be sized appropriately for actual needs rather than pessimistic assumptions, maintaining voltage stability while reducing die area.
Data Source
AI summary
Various embodiments of the disclosure disclosed herein provide techniques for pre-silicon testing of a design for an integrated circuit. A pre-silicon testing system identifies one or more critical paths included in the integrated circuit. The pre-silicon testing system performs a based noise simulation to generate one or more voltage waveforms at each gate associated with the one or more critical paths. The pre-silicon testing system applies the one or more voltage waveforms to one or more netlists corresponding to the one or more critical paths to generate one or more modified netlists. The pre-silicon testing system performs a timing analysis on the one or more modified netlists to determine a set of slack times that correspond to a set of voltages applied to the integrated circuit. The pre-silicon testing system determines a first critical path that has a lowest slack time relative to all other critical paths.