Pre-Spacer Cut Gate Structures for Tight IC Gate Spacing
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Solution Overview
Problem
The challenge of scaling multi-gate and nanowire transistors to smaller dimensions is hindered by constraints on lithographic processes, leading to issues with critical dimension and spacing between features, which affect transistor performance and density.
Innovation Solution
Implementing a narrow poly (gate) cut after hardmask patterning or poly etch, followed by spacer deposition, allows for precise patterning of very small critical dimensions and simplifies the process flow, enabling cost-effective fabrication of gate-all-around devices with reduced gate height loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern multi-gate transistors, then feature patterning can be achieved, but the spacing between features and critical dimension control deteriorate as scaling continues
Solution Approach 1:
The gate pattern is formed preliminarily through hardmask patterning or poly etch before spacer deposition. This preliminary gate structure serves as a template that defines the precise critical dimensions, allowing subsequent spacer formation to automatically establish the correct spacing between features without requiring additional lithographic steps at the same resolution
Solution Approach 2:
A spacer material is introduced as an intermediary element between the preliminarily formed gate patterns. The spacer deposition process uses the gate structure itself as a mask or template, allowing the spacer to self-align and automatically establish precise spacing. This intermediary approach transfers the patterning task from direct lithographic feature creation to spacer-based spacing definition
2Productivity
If narrow poly cuts are implemented after hardmask patterning, then transistor density increases, but process complexity increases
Solution Approach 1:
The narrow poly cut operation is merged with the existing hardmask patterning or poly etch process flow. Rather than adding a separate, complex lithographic step, the poly cut is integrated into the already-planned process sequence, utilizing the same equipment and process parameters where feasible. This merging approach increases transistor density while minimizing the addition of process complexity
Data Source
AI summary
Integrated circuit structures having pre-spacer-deposition cut gates and associated defect test structures are described. For example, an integrated circuit structure includes a first and second fin or vertical arrangement of horizontal nanowires. First and second gate stacks are over the first and second fin or vertical arrangement of horizontal nanowires, respectively. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A dielectric structure has first and second portions forming a gate spacer along sidewalls of the first and second gate stacks, respectively, and a third portion completely filling the gap, the third portion continuous with the first and second portions. The integrated circuit structure also includes an array having a periodic arrangement of alternating floating and grounded conductive trench contacts along a direction parallel with the first gate stack and the second gate stack.