Pre-staged Instruction Registers for Variable Length ISAs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing computer processing architectures face inefficiencies in energy consumption and instruction transmission due to the need for larger instruction sizes and more specialized instructions, which increase costs and complexity.
Innovation Solution
A processing architecture that dynamically creates compound instructions, allowing for the execution of multiple operations using the power and bus size associated with a single instruction, by pre-staging instructions in registers and triggering their execution with a single instruction from memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If larger instruction sizes are used to include more specialized instructions, then more operations can be performed per instruction, but the bus size, register size, and logic complexity increase
Solution Approach 1:
The instruction stream is segmented into two types: compact component instructions (small size) and compound instructions (larger size). The compound instructions are broken down into multiple component instructions that are executed sequentially. This segmentation allows the system to achieve high productivity through compound instructions while keeping the basic instruction format compact, thus resolving the contradiction between operations per instruction and device complexity.
Solution Approach 2:
The compound instructions are pre-decoded into sequences of component instructions and stored in the instruction cache. When a compound instruction is encountered, the pre-decoded component instructions are retrieved and executed, eliminating the need for real-time decoding of complex instructions. This preliminary action reduces the logic complexity required for instruction decoding while maintaining the ability to execute multiple operations per compound instruction.
2Loss of time
If more specialized instructions are included in the instruction set, then fewer instructions need to be transmitted, but a larger library of instructions and more complex functional processing units are required
Solution Approach 1:
A small set of universal functional processing units is designed to execute the compact component instructions. By making these units multi-functional, the system can perform a wide variety of operations without requiring specialized hardware for each instruction type. The compound instructions achieve specialization through software-based composition of these universal units, reducing both the instruction library size and hardware complexity while minimizing the number of instructions that need to be transmitted.
Solution Approach 2:
Instead of transmitting large compound instructions repeatedly, the system transmits a compact compound instruction once, which is then decoded and cached as a sequence of component instructions. These cached component instructions are reused for subsequent executions, reducing transmission overhead. This copying approach minimizes the number of instructions transmitted while avoiding the need for a large specialized instruction library.
3Productivity
If a variable length instruction set machine is implemented, then more operations can be performed per instruction, but the instruction bus size increases
Solution Approach 1:
The instruction set dynamically adapts its effective length based on the instruction type. Compound instructions can be longer when needed to specify multiple operations, while simple component instructions remain short. The system dynamically selects between using pre-decoded cached instructions (effectively shorter transmission) and transmitting new compound instructions only when necessary. This dynamic approach allows high productivity through compound instructions while keeping the average instruction bus size manageable.
Data Source
AI summary
Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes a memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.