Pre-tracing Instructions for CGA Coupled Processor Cache Misses

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Solution Overview

Problem

Conventional reconfigurable processor architectures face challenges in reducing cache misses, which lead to increased instruction performance cycles and penalties due to prediction failures, especially when accessing memory.

Innovation Solution

A processor architecture with an active and inactive mode, where the instruction cache pre-traces instructions during the inactive mode and generates a pseudo program counter value to detect cache misses, allowing for efficient storage and retrieval of instructions from external memory, thereby minimizing cache misses and reducing instruction performance cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the processor uses a cache memory system to improve access speed, then data access time is reduced, but cache misses occur leading to performance penalties

Engineering Contradiction:

Improvedata access timeVSAvoidcache hit ratio

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-fetching instructions into the instruction cache during the inactive mode of the processor core, before they are actually needed during active mode. This advance preparation ensures that instructions are already in the cache when needed, eliminating cache misses and their associated performance penalties while maintaining fast access times

Inventive Principle:

Principle #10Preliminary action

2Productivity

If the processor operates in processor core mode with traditional cache management, then instruction execution is performed, but cache misses increase instruction performance cycles

Engineering Contradiction:

Improveinstruction execution throughputVSAvoidinstruction performance cycle

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The system performs preliminary action by utilizing the inactive mode to pre-fetch and load instructions into the instruction cache in advance. This eliminates wait states and performance cycle extensions caused by cache misses during active instruction execution, thereby improving overall productivity without increasing execution time

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuity of useful action by ensuring that the instruction cache is continuously populated with upcoming instructions during inactive periods. This continuous preparation eliminates interruptions and performance cycle extensions that would otherwise occur when cache misses happen during active execution

Inventive Principle:

Principle #20Continuity of useful action

3Reliability

If the processor uses predictive algorithms to pre-fetch instructions, then future cache misses are reduced, but prediction failures cause penalties

Engineering Contradiction:

Improvecache hit ratioVSAvoidprediction mechanism complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action without prediction by systematically loading instructions into the cache during inactive mode based on known program counter sequences. This deterministic approach avoids the complexity of predictive algorithms and their associated failure penalties, achieving reliable cache hits through advance preparation rather than prediction

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system uses a simple, lightweight pre-fetch mechanism during inactive mode that does not require complex predictive algorithms. This simpler, less resource-intensive approach achieves the same goal of reducing cache misses without the overhead and potential failures of sophisticated prediction systems

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

4Use of energy by moving object

If the processor core is in inactive mode, then power consumption is reduced, but instruction pre-fetching opportunities are lost

Engineering Contradiction:

Improveprocessor power consumptionVSAvoidinstruction pre-fetch efficiency

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent leverages the inactive mode period to perform preliminary action by pre-fetching instructions into the cache. This transforms the low-power inactive state into a productive time for instruction preparation, ensuring that when the processor transitions to active mode, instructions are already cached and ready for immediate execution without compromising power efficiency

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7836277B2Pre-tracing instructions for CGA coupled processor in inactive mode for execution upon switch to active mode and continuing pre-fetching cache miss instructions

Publication Date: 2010.11.16 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of managing an instruction cache and a process of using the method are provided. The processor may comprise a processor core which is operated either during an active mode or during an inactive mode wherein the process core performs at least one instruction during the active mode, an instruction cache which pre-traces a first instruction and determines, during the inactive mode, whether the processor core will meet a cache miss with regard to the first instruction, wherein the first instruction is to be performed by the processor core during the active mode, a coarse-grained array which performs a second instruction during the inactive mode, and a configuration memory which stores configuration information of the coarse-grained array, wherein the coarse-grained array performs the second instruction using the configuration information.