Pre-applied Underfill for Flip Chip Alignment

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Solution Overview

Problem

Current flip chip technology faces challenges in achieving high throughput and minimizing filler inclusions in underfill connections due to the difficulty in aligning pre-applied underfill on substrates, which increases costs and complicates the joining process, especially for multi-chip modules and CSP applications.

Innovation Solution

The development of columnar solder bumps or metal columns on substrates or chips, combined with a pre-applied underfill that minimizes the over-bumped amount of underfill, allowing for easy automatic alignment and reducing the thickness of the underfill layer, thereby minimizing filler inclusions and enhancing assembly yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If pre-applied underfill is used on substrates, then alignment between chip and substrate can be achieved, but the alignment process becomes complex and costly

Engineering Contradiction:
Improvealignment precisionVSAvoidalignment process complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The underfill material is pre-applied to the substrate surface before chip placement, creating a ready-to-use alignment medium that simplifies the subsequent bonding process while maintaining precise alignment capabilities through the material's optical properties

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pre-applied underfill acts as an intermediary layer between the chip and substrate, providing both mechanical support and optical contrast for alignment marks, thereby mediating the alignment process and reducing overall system complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If pre-applied underfill is used on substrates, then joining process can be simplified, but filler inclusions in underfill connections increase

Engineering Contradiction:
Improvejoining process easeVSAvoidsolder joint reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The viscosity of the underfill material is carefully controlled and optimized to allow proper flow and filling of gaps during bonding while preventing excessive resin displacement that would cause filler inclusions, thereby maintaining solder joint reliability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The pre-applied underfill layer is applied with controlled thickness and coverage, providing sufficient material to fill gaps and accommodate thermal expansion without excessive amounts that would lead to resin entrapment and filler inclusions during the bonding process

Inventive Principle:
Principle #16Partial or excessive action

3Quantity of substance

If taller bumps are used, then sufficient underfill can be accommodated, but resin displacement increases

Engineering Contradiction:
Improveunderfill quantityVSAvoidresin displacement
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The viscosity and flow characteristics of the underfill material are optimized to match the height and geometry of the taller bumps, allowing the material to properly fill gaps and accommodate the increased volume without excessive displacement or entrapment during bonding

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach broadens the processing window for flip chip assembly, enabling faster alignment and higher reliability of solder joints with reduced underfill inclusion, leading to improved assembly yields and lower costs by allowing taller bumps to accommodate sufficient underfill without excessive resin displacement.

Implementation Method 1

a pre-applied underfill that minimizes the over-bumped amount of underfill, allowing for easy automatic alignment and reducing the thickness of the underfill layer, thereby minimizing filler inclusions

Methodology Applied
Scientific EffectFlow:

Implementation Method 2

enabling faster alignment and higher reliability of solder joints with reduced underfill inclusion, leading to improved assembly yields and lower costs by allowing taller bumps to accommodate sufficient underfill without excessive resin displacement

Methodology Applied
Scientific EffectHeating: Heating

Data Source

PatentUS9305896B2No flow underfill or wafer level underfill and solder columns
Publication Date: 2016.04.05 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9305896B2 patent drawing
  • US9305896B2 patent drawing
  • US9305896B2 patent drawing

AI summary

A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures. In another embodiment the height of the chip soldering structures is greater than the height of the substrate soldering structures and the pre-applied underfill is contiguous with the semiconductor chip and sufficiently thick so as to extend substantially no further than the full height of the chip soldering structures. A process comprises manufacturing semiconductor assemblies from these devices by soldering the chip and the substrate to one another