Pre-bump Circuit Board Structure for Flip Chip Alignment
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Solution Overview
Problem
The existing flip chip interconnect technology faces challenges with solder bump collapse during the bonding process, leading to reduced manufacturing yield due to alignment accuracy requirements, which restricts the reduction of bump pitches and contact density between chip pads.
Innovation Solution
A circuit board structure with pre-bumps having a protrusion that protrudes from the top solder resist layer, where the maximum width of the protrusion is less than or equal to the width of the top pad, allowing for reduced dimensions and shorter bump pitches without compromising alignment accuracy, achieved through electroplating on a conductive layer formed on the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the openings of the patterned photoresist layer are completely exposed to ensure connection with solder resist layer openings, then alignment accuracy requirements are reduced, but the width of the photoresist openings cannot be reduced, preventing reduction of bump pitches
Solution Approach 1:
The solder resist layer openings are formed first to expose the pads, and then the photoresist layer openings are formed to connect with these pre-formed openings. This preliminary action allows the photoresist openings to be precisely aligned with the solder resist openings, ensuring connection while enabling reduction of photoresist opening width and bump pitch.
Solution Approach 2:
The photoresist layer openings are designed with different width characteristics at different locations: wider at the bottom to ensure connection with solder resist openings, and narrower at the top to enable reduced bump pitch. This local quality variation resolves the contradiction between alignment accuracy and bump pitch reduction.
2Volume of moving object
If solder bumps are used for bonding chip to chip carrier in flip chip interconnect, then miniaturized chip package size and shortened signal transmission path are achieved, but the solder bumps are apt to be squeezed and collapsed, reducing manufacturing yield
Solution Approach 1:
Pre-bumps are formed on the chip carrier before the chip is mounted. These pre-bumps protrude from the chip carrier surface and are positioned to support the solder bumps during the flip chip interconnect process. This preliminary action provides mechanical support that prevents solder bump collapse, thereby improving manufacturing yield while maintaining miniaturized chip package size.
3Quantity of substance
If the width of photoresist openings is reduced to enable smaller bump pitches, then contact density is improved, but alignment accuracy requirements become more stringent, complicating the formation process
Solution Approach 1:
The solder resist layer openings are formed first to establish precise pad locations, and then the photoresist layer openings are formed to connect with these pre-defined locations. This sequential approach allows narrow photoresist openings to be accurately aligned with the broader solder resist openings, enabling high contact density without excessive alignment stringency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces pre-bump dimensions and shortens bump pitches, enhancing contact density and manufacturing yield by eliminating alignment accuracy limitations, enabling smaller chip pad pitches and improved signal transmission.
Implementation Method 1
by electroplating the seed layer, the openings of the solder resist layer and the openings of the patterned photoresist layer are filled with metal, so as to form the pre-bumps
Data Source
AI summary
A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.