Precharge Capacitor Switch Matrix for Memory Voltage Generation
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Solution Overview
Problem
Current memory technologies face challenges in efficiently providing multiple voltage levels to memory cells, leading to increased manufacturing costs and power consumption due to the need for multiple voltage levels, which can be generated on-chip or received from off-chip sources.
Innovation Solution
The implementation of a charge sharing technique that uses a precharge capacitor and a switch matrix to provide arbitrary voltages to a high impedance node of a memory cell, allowing for the generation of desired voltage levels without the need for multiple voltage sources, thereby reducing power consumption and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple voltage levels are provided to memory cells, then memory performance and density are improved, but power consumption and manufacturing cost increase
Solution Approach 1:
The memory device generates its own multiple voltage levels internally using a charge pump circuit, eliminating the need for external voltage sources. The generated voltages are stored in capacitors and selectively applied to memory cells, enabling the device to serve its own voltage requirements without external support.
2Productivity
If multiple voltage levels are generated on-chip, then memory performance is improved, but power consumption and die-area increase
Solution Approach 1:
The patent combines multiple voltage generation and distribution functions into a single integrated circuit block. The charge pump, voltage storage capacitors, and voltage selection logic are merged into one compact unit that can serve multiple memory cells, minimizing the overall die-area required for voltage generation.
3Productivity
If multiple voltage levels are received from off-chip sources, then memory performance is improved, but packaging and manufacturing cost increase
Solution Approach 1:
The patent extracts the voltage generation function from external sources and relocates it entirely within the memory device. By removing the dependency on off-chip voltage sources, the design eliminates the need for multiple external pins and associated packaging complexity, thereby reducing manufacturing costs.
4Adaptability or versatility
If charge pump or tank capacitor is used for voltage generation, then multiple voltage levels are achieved, but power consumption increases
Solution Approach 1:
The charge pump circuit operates in periodic cycles, alternating between charging capacitors to desired voltage levels and then selectively discharging them to memory cells. This periodic operation allows the system to generate multiple voltage levels while minimizing continuous power consumption, as the pump only activates when voltage replenishment is needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient generation and delivery of multiple voltage levels to memory cells, reducing power consumption and manufacturing costs while maintaining the complexity of memory devices, thereby addressing the limitations of existing memory technologies.
Implementation Method 1
a precharge capacitor coupled to the precharge switch
Implementation Method 2
a switch matrix coupled to the precharge capacitor, a second voltage source node, and the high impedance node of the memory cell
Data Source
AI summary
Techniques for accessing memory cells are disclosed. In one particular embodiment, the techniques may be realized as an apparatus providing voltage to a high impedance node of a memory cell. The apparatus may comprise a precharge switch coupled to a first voltage source node, a precharge capacitor coupled to the precharge switch, and a switch matrix coupled to the precharge capacitor, a second voltage source node, and the high impedance node of the memory cell. The precharge switch may be configured to decouple the precharge capacitor from the first voltage source node, and the switch matrix may be configured to decouple the second voltage source node from the high impedance node of the memory cell and to couple the precharge capacitor to the high impedance node of the memory cell.