Precharge Circuit for SRAM Bit Line Sensing Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
SRAM cells in CMOS image sensors experience value distortion due to high voltage and large loading capacitance, leading to errors in data sensing, particularly at the Fast-Slow corner, which can render entire chip defective and affect yield.
Innovation Solution
A precharge circuit that controls precharge time based on the threshold voltage of a transistor, using a precharge time controller to generate a control signal for precharging bit lines and bit line bars, ensuring accurate data sensing by adjusting precharge and sensing periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If precharge time is extended to ensure accurate sensing, then sensing accuracy is improved, but the stored value in SRAM cell may change due to high voltage
Solution Approach 1:
The precharge time is made dynamic rather than fixed, adjusting the precharge duration based on detected transistor characteristics. The circuit selectively extends or reduces precharge time for specific SRAM cells depending on their individual threshold voltage profiles, allowing each cell to receive optimized precharge duration that prevents value distortion while ensuring accurate sensing.
Solution Approach 2:
The invention changes the precharge time parameter based on transistor threshold voltage characteristics. By detecting whether a transistor has high or low threshold voltage, the circuit modifies the precharge time parameter accordingly - using shorter precharge times for cells with high threshold voltage transistors and longer precharge times for cells with low threshold voltage transistors.
2Reliability
If precharge time is shortened to prevent value distortion, then stored value stability is improved, but sensing accuracy deteriorates
Solution Approach 1:
The precharge time is dynamically adjusted based on real-time detection of transistor characteristics. Rather than using a conservative fixed short precharge time for all cells, the circuit adapts the precharge duration to each cell's specific needs, extending it when necessary for accurate sensing while preventing excessive duration that would cause value distortion.
Solution Approach 2:
The invention modifies the precharge time parameter based on detected transistor threshold voltage characteristics. By changing the precharge time parameter selectively for different SRAM cells, the system optimizes the balance between preventing value distortion and ensuring sufficient sensing accuracy for each individual cell.
3Device complexity
If fixed precharge time is used for all SRAM cells, then device complexity is reduced, but manufacturing precision deteriorates due to transistor characteristic variations
Solution Approach 1:
The SRAM cell itself provides information about its characteristics through its threshold voltage, which the detection circuit reads to determine the appropriate precharge time. The cell essentially serves itself by providing the data needed to optimize its own operation, eliminating the need for external characterization and manual configuration.
Solution Approach 2:
The invention implements a feedback mechanism where the detection circuit monitors transistor threshold voltage characteristics and uses this information to adjust the precharge time control signal. This closed-loop feedback ensures that each SRAM cell operates with optimized parameters based on its actual characteristics, improving manufacturing precision without significantly increasing overall system complexity.
Data Source
AI summary
A precharge circuit includes: a precharge time controller suitable for generating a precharge time control signal based on a threshold voltage of a transistor; a precharge control signal generator suitable for generating a precharge control signal activated during a predetermined period based on the precharge time control signal from the precharge time controller; and a precharger suitable for precharging a bit line and a bit line bar during the predetermined period based on the precharge control signal from the precharge control signal generator.