Precharge Elimination Circuit for ESD Protection
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Solution Overview
Problem
Integrated circuits (ICs) are vulnerable to false electrostatic discharge (ESD) testing results due to noise pulses generated by high pin-count testers, leading to misleading evaluations and potential damage from trailing pulses that cause oxide stress.
Innovation Solution
The implementation of precharge elimination circuits in ICs, powered by the same VDD, which include resistors, nMOS transistors, and RC timers, synchronize with ESD protection circuits to discharge any spurious voltage build-up before an ESD event, ensuring undiminished ESD protection capability and preventing false failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high pin-count testers are used to evaluate semiconductor products, then testing coverage is improved, but noise pulses are generated that cause false ESD failure declarations
Solution Approach 1:
The precharge elimination circuit proactively removes spurious precharge voltages before they can interfere with the ESD protection circuit operation. By detecting and discharging accumulated charges on the pad through a controlled path during normal operation, the circuit prevents the formation of conditions that would lead to false failure declarations during testing.
Solution Approach 2:
The precharge elimination circuit acts as an intermediary between the high pin-count tester and the ESD protection circuit. It absorbs and dissipates the noise pulses and precharge voltages generated by the tester before they can reach and falsely trigger the ESD protection circuit, thereby maintaining test result accuracy while allowing comprehensive testing.
2Reliability
If precharge voltages are not eliminated, then the ESD protection circuit may be falsely triggered, but adding precharge elimination circuits increases device complexity
Solution Approach 1:
The precharge elimination function is merged with the existing ESD protection circuit structure. The elimination circuit uses the same power supply (VDD) and shares common nodes with the ESD protection circuit, allowing both functions to coexist in a unified design that minimizes additional complexity while ensuring reliable ESD protection.
Solution Approach 2:
The precharge elimination circuit is designed to automatically detect and eliminate precharge voltages without requiring external control signals or additional complex logic. The circuit self-regulates by monitoring the pad voltage and activating the discharge path when precharge conditions are detected, reducing the need for additional control circuitry.
3Reliability
If precharge elimination circuits are added, then false ESD failures are prevented, but manufacturing cost increases
Solution Approach 1:
The precharge elimination circuit employs simple, inexpensive components such as resistors, capacitors, and standard nMOS transistors that can be easily manufactured using existing CMOS fabrication processes. These components are designed to be functional rather than durable, serving their purpose of eliminating precharge voltages during testing without requiring high-cost materials or complex manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The precharge elimination circuits effectively eliminate precharge voltages, preventing false ESD failures and ensuring accurate testing results by maintaining the full strength of ESD protection, thus enhancing the reliability of ESD evaluation and reducing resource wastage and customer misunderstandings.
Implementation Method 1
the precharge elimination circuit is operable to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad
Implementation Method 2
A first RC timer is connected to the first nMOS transistor gate; the first RC timer includes a second resistor connected to ground and a first capacitor connected to VDD
Implementation Method 3
An ESD protection circuit is between VDD and ground potential, whereby the ESD protection circuit is in parallel with the first and the second precharge elimination circuit
Data Source
AI summary
An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).