Precharge Switch-Capacitor Circuit for High Input Impedance
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Solution Overview
Problem
Faster sampling frequency and larger input sampling capacitors in conventional switched-capacitor circuits result in lower input impedance, leading to accuracy issues in performance metrics such as gain error, gain error temperature drift, and non-linearity due to loading effects, and high power dissipation from precharge buffer settling.
Innovation Solution
The proposed switched-capacitor circuit design includes a precharge buffer and a precharge switch-capacitor circuit with multiple capacitors and switches, allowing for a longer precharge buffer settling time while maintaining high input impedance by optimizing switch timing and capacitor connections during coarse and fine sampling phases, thereby reducing power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If faster sampling frequency and larger input sampling capacitors are used in conventional switched-capacitor circuits, then sampling speed and capacitance are improved, but input impedance decreases leading to accuracy issues and high power dissipation
Solution Approach 1:
The sampling process is divided into two distinct phases: a coarse sampling phase where the sampling capacitor is connected to the input through a switch, and a fine sampling phase where the sampling capacitor is connected to the input through a buffered path. This segmentation allows the circuit to achieve both fast sampling (coarse phase) and high accuracy (fine phase) without compromising input impedance, as each phase can be optimized independently for its specific function.
2Measurement precision
If precharge buffer settling time is extended, then accuracy is improved, but power dissipation increases
Solution Approach 1:
The circuit employs periodic switching between coarse and fine sampling phases. During the coarse sampling phase, the sampling capacitor is quickly charged to the input voltage level. During the fine sampling phase, the buffer amplifier settles the sampling capacitor to the precise input voltage level. This periodic action allows the buffer to settle only during the fine sampling phase rather than continuously, reducing power dissipation while maintaining settling accuracy.
3Measurement precision
If fine sampling phase is lengthened, then sampling accuracy is improved, but overall sampling rate decreases
Solution Approach 1:
The sampling process is segmented into a short coarse sampling phase for rapid voltage acquisition and a longer fine sampling phase for high-precision settling. The coarse phase captures the majority of the voltage transition quickly, while the fine phase completes the precise settling. This segmentation allows the fine sampling phase to be lengthened for accuracy without proportionally reducing the overall sampling rate, as the coarse phase compensates by completing much of the voltage transfer rapidly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases the input impedance of the switched-capacitor circuit while minimizing precharge buffer power dissipation, improving accuracy and reducing power consumption by extending the precharge buffer settling time and lengthening the fine sampling phase.
Implementation Method 1
a first capacitor and a second capacitor configured such that the first and second capacitors are connected in series during a coarse sampling time and in parallel during a fine sampling time and charge transfer time
Data Source
AI summary
An input sampling stage circuit includes, a precharge buffer, a precharge switch-capacitor circuit, and an input sampling capacitor. The precharge buffer is configured to buffer an input voltage. The precharge switch-capacitor circuit includes a plurality of switches, a first capacitor, and a second capacitor configured such that the first and second capacitors are connected in series during a coarse sampling time and in parallel during a fine sampling time and charge transfer time. The input sampling capacitor is configured to sample the input voltage through the precharge switch-capacitor circuit during the coarse sampling time and sample the input voltage directly during the fine sampling time.