Pre-Charged Capacitor DAC for Faster Settling in SAR ADCs
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Solution Overview
Problem
Charge redistribution digital-to-analog converters (DACs) in integrated circuits are limited by parasitic inductances, which restrict their settling speed, especially in high-speed applications like successive approximation (SAR) ADCs.
Innovation Solution
A charge redistribution DAC design that integrates two sets of capacitors, allowing charge sharing between pairs of capacitors instead of using traditional external reference voltages, with bridging switches to short the second sides of capacitors, improving settling speed by reducing the impact of parasitic inductances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional charge redistribution DAC design with external reference voltages is used, then the circuit structure is simple, but the parasitic inductances limit the settling speed
Solution Approach 1:
The patent segments the capacitor array into multiple groups, with each group having its own reference voltage source. This segmentation allows independent charge redistribution in each group, reducing the overall settling time while maintaining the basic charge redistribution DAC structure
Solution Approach 2:
The patent pre-charges the capacitors to reference voltages before the actual DAC conversion process. This preliminary action prepares the capacitors in advance, allowing faster settling during the actual conversion by reducing the charge redistribution distance and time
2Productivity
If charge redistribution is performed with external reference voltages, then the implementation is straightforward, but parasitic inductances cause ringing and limit operating frequency
Solution Approach 1:
The patent extracts and eliminates the need for external reference voltage sources by integrating reference voltage generation within the DAC structure. This removes the parasitic inductances associated with external connections, allowing higher operating frequencies without ringing
Solution Approach 2:
The patent merges the reference voltage sources with the capacitor array structure, creating an integrated design where reference voltages are generated locally. This consolidation eliminates external parasitic inductances and reduces the overall settling time
3Loss of time
If high-speed operation is required, then the settling speed must be improved, but parasitic inductances in the circuit limit the maximum achievable speed
Solution Approach 1:
The patent implements dynamic switching of capacitor connections during the charge redistribution process. This dynamic approach allows the circuit to adaptively optimize the charge transfer paths, reducing settling time while maintaining stable and reliable operation through controlled switching sequences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the settling speed of the DAC, thereby improving the performance of SAR ADCs by minimizing the influence of parasitic inductances, allowing for higher frequency operation.
Implementation Method 1
The DAC 200 includes two sets of binary-weighted capacitors 202.1-202.N and 204.1-204.N
Implementation Method 2
A first switch 222.1-222.N selectively couples a first side of each capacitor 202.1-202.N and 204.1-204.N to a common mode voltage
Data Source
AI summary
Embodiments of the present disclosure may provide a charge redistribution DAC with two sets of capacitors that provides a DAC output by sharing charges between a plurality of pairs of capacitors in lieu of charging the capacitors using traditional external reference voltages. The charge redistribution DAC may comprise a plurality of pairs of first and second capacitors that each has a first side and a second side, and a group of first switches and a group of second switches. Each first or second switch selectively controls connection of the first side of a respective first or second capacitor to one of a pair of output signal lines according to a DAC input word. The charge redistribution DAC further may comprise a group of bridging switches each connected between second sides of paired first and second capacitors.