Pre-Charged Capacitive DAC for Faster Settling in SAR ADCs
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Solution Overview
Problem
Charge redistribution digital-to-analog converters (DACs) in integrated circuits face limitations due to parasitic inductances, which restrict their settling speed, especially in high-speed applications like successive approximation (SAR) ADCs.
Innovation Solution
A charge redistribution DAC design that integrates two sets of capacitors, allowing charge sharing between pairs of capacitors instead of using traditional external reference voltages, with bridging switches to short the second sides of capacitors, improving settling speed by reducing the impact of parasitic inductances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional external reference voltages are used for charging capacitors, then the DAC structure is simple, but the settling speed is limited due to parasitic inductances
Solution Approach 1:
The capacitor array is divided into two sets (first set and second set) where each set contains capacitors that can be independently controlled. This segmentation allows differential charging paths that cancel parasitic inductance effects, thereby improving settling speed while maintaining manageable structural complexity through systematic organization.
Solution Approach 2:
A reservoir capacitor is introduced as an intermediary element to facilitate charge redistribution between the first and second sets of capacitors. This mediator enables the charge sharing mechanism that eliminates the need for external reference voltages during the redistribution phase, thus improving settling speed without proportionally increasing complexity.
2Productivity
If parasitic inductances are present in reference voltage connections, then the circuit implementation is straightforward, but the maximum operating frequency is limited
Solution Approach 1:
The patent converts the harmful effect of parasitic inductances into a beneficial differential mode operation. By using two sets of capacitors with opposite polarity connections, the parasitic inductances in the two paths experience equal but opposite voltage changes, causing their effects to cancel out. This allows the circuit to operate at higher frequencies despite the presence of parasitic inductances.
Solution Approach 2:
The invention changes the operating parameters by transitioning from single-ended reference voltage charging to differential charge redistribution. This parameter change involves switching between two distinct operational modes (charging phase with external references and redistribution phase with internal charge sharing), thereby eliminating the frequency-limiting effect of parasitic inductances in the reference voltage paths.
3Loss of time
If charge redistribution is performed using external reference voltages, then the circuit design is simple, but the settling time is prolonged
Solution Approach 1:
The patent merges the functions of charge storage and charge redistribution into a unified capacitor array structure. By integrating two sets of capacitors that can perform both charging from external references and internal charge redistribution through bridging switches, the design eliminates the need for separate reference voltage connections during redistribution, thereby reducing settling time while consolidating the switching network functionality.
Solution Approach 2:
During the charging phase, capacitors in the first and second sets are pre-charged to complementary voltage levels using external reference voltages. This preliminary action stores the necessary charge differentials in advance, so that during the redistribution phase, only simple switching and charge sharing are needed rather than active charging, significantly reducing the settling time required for the final voltage establishment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the settling speed of the DAC, thereby improving the performance of SAR ADCs by minimizing the effects of parasitic inductances, allowing for higher frequency operation.
Implementation Method 1
charge redistribution DAC design that integrates two sets of capacitors, allowing charge sharing between pairs of capacitors
Implementation Method 2
bridging switches to short the second sides of capacitors
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
Embodiments of the present disclosure may provide a charge redistribution DAC with two sets of capacitors that provides a DAC output by sharing charges between a plurality of pairs of capacitors in lieu of charging the capacitors using traditional external reference voltages. The charge redistribution DAC may comprise a plurality of pairs of first and second capacitors that each has a first side and a second side, and a group of first switches and a group of second switches. Each first or second switch selectively controls connection of the first side of a respective first or second capacitor to one of a pair of output signal lines according to a DAC input word. The charge redistribution DAC further may comprise a group of bridging switches each connected between second sides of paired first and second capacitors.