Precharged Level Shifter Layout for Smaller Memory Circuits
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Solution Overview
Problem
Conventional level shifters in high-density memory architectures face limitations due to the size relationship between override and hold circuits, restricting the ability to reduce the surface area, as they require greater drive strength to overpower hold devices, leading to increased size and area constraints.
Innovation Solution
The proposed solution involves a level shifter design with precharge circuits that precharge level shift circuits to facilitate output signal transitions, allowing for reduced surface area by optimizing the size relationship between override and hold devices through the use of NOR and NAND gates, transistors, and specific voltage configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shifters use override circuits with greater drive strength than hold circuits, then proper voltage level shifting operation is achieved, but the surface area of the level shifter increases
Solution Approach 1:
The patent applies preliminary action by precharging the output node to the higher voltage level before the override circuit needs to override it. This precharging is done through a precharge transistor that is activated in advance, ensuring the output node is already at the target voltage level, thereby reducing the drive strength requirement for the override circuit and allowing for smaller device sizes.
Solution Approach 2:
The patent implements dynamics by using different transistor size relationships for different operational phases. During the precharge phase, the precharge transistor is sized to efficiently charge the output node. During the override phase, the override transistor is sized appropriately for the reduced charging requirement. This dynamic sizing approach allows optimization of surface area while maintaining proper operation throughout different operational states.
2Reliability
If the size relationship between override devices and hold devices is constrained for proper operation, then voltage override capability is maintained, but the ability to reduce surface area is limited
Solution Approach 1:
The precharge transistor charges the output node to the higher voltage level in advance, before the override operation begins. This preliminary charging action reduces the amount of charge the override transistor needs to supply during the actual override phase, allowing the override transistor to be smaller than it would be without precharging, thus enabling surface area reduction while maintaining override capability.
3Quantity of substance
If high density memory architectures are implemented, then memory capacity increases, but physical characteristics of smaller circuit devices become incapable of performing desired functions
Solution Approach 1:
The precharge transistor performs preliminary charging of the output node to the higher voltage level before the override operation. This ensures that even smaller transistors in high-density architectures can achieve the necessary voltage levels, as the precharge transistor has already established the target voltage, reducing the burden on the override transistor and enabling proper functionality with smaller device sizes.
Data Source
AI summary
Apparatuses and methods, such as those for shifting a voltage level are disclosed. An example apparatus includes a level shifter configured to provide output signals based on a logical value of an input signal, where the level shifter is precharged to a precharge voltage prior to providing the output signals. An example method includes precharging an output node of a level shifter to a precharge voltage responsive to a precharge signal via a precharge circuit. A transition of the input signal from a first logical value to a second logical value is received at the level shifter and an output signal is provided at the output node based on the second logical value of the input signal.