On-Chip Precision Buffer Switching for Fast Switched Loads
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Solution Overview
Problem
High-speed buffers face challenges in balancing precision and speed requirements when driving switched loads, with open-loop designs sacrificing precision and closed-loop designs sacrificing speed, and existing solutions often require additional pins and external components.
Innovation Solution
A precision buffer system that includes auto-zeroing and chopper-stabilized main and replica buffers, with a backend calibration circuit, allowing for low-bandwidth high-gain feedback and eliminating the need for external components by isolating the feedback loop during switched-load events, enabling both high precision and speed without additional pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If open-loop buffer is used to drive switched loads, then speed requirement is met, but precision requirement deteriorates due to deviations from desired output voltage
Solution Approach 1:
The patent segments the buffer operation into two distinct modes: open-loop mode for speed-critical switched-load driving and closed-loop mode for precision-critical steady-state operation. The switching mechanism transitions between these modes based on operational requirements, allowing the system to achieve both high speed and high precision at different times without compromise
Solution Approach 2:
The patent implements dynamic switching between open-loop and closed-loop configurations. The buffer operates in open-loop during switched-load events for maximum speed, then transitions to closed-loop for precision settling. This dynamic reconfiguration resolves the static contradiction between speed and precision requirements
2Measurement precision
If closed-loop buffer is used to drive switched loads, then precision requirement is met, but speed requirement deteriorates due to feedback loop limitations
Solution Approach 1:
The patent segments the buffering function between open-loop and closed-loop paths. The open-loop path handles high-speed switched-load current delivery while the closed-loop path handles precision voltage regulation during steady-state, eliminating the need for the closed-loop to compete with switched-load speed requirements
Solution Approach 2:
The patent extracts the high-speed switched-load driving function from the closed-loop feedback path and assigns it to the open-loop buffer. This extraction allows the closed-loop to operate at lower bandwidth for precision without being constrained by switched-load speed requirements
3Quantity of substance
If external capacitors are used to deliver charge to switched-load, then charge delivery capability is improved, but device complexity increases due to additional pins and external components
Solution Approach 1:
The patent merges the charge storage function with the buffer output node by utilizing the inherent output capacitance and integrating on-chip compensation capacitors. This eliminates the need for separate external capacitors and reduces pin count while maintaining adequate charge delivery capability for switched-loads
Solution Approach 2:
The patent makes the buffer output node multi-functional by using it both as the voltage output node and as the charge storage node for switched-load events. This universal usage eliminates the need for dedicated external charge storage components
Data Source
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AI summary
A buffer system may have an output for driving a switched load that changes during periods indicated by a switching signal. The buffer system may operate in a closed loop when the switching signal indicates that a load change is not taking place by comparing a signal indicative of the output of the buffer system with a reference voltage. The buffer system may operate in an open loop when the switching signal indicates that a load change is taking place by not comparing signal indicative of the output of the buffer system with the reference voltage. Both the buffer system and the switched load may be on the same chip.