Precision Resistor in SAGE Architecture via Blocked DEPOP
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Solution Overview
Problem
Conventional precision resistors in integrated circuit fabrication face challenges such as high variation and temperature coefficients, leading to increased costs and complexity, especially in high-k/metal gate process technologies, and are difficult to integrate with self-aligned gate endcap (SAGE) architectures.
Innovation Solution
A cost-effective precision resistor is fabricated using a blocked Dry Etch Poly Open Polish (DEPOP) method within a SAGE architecture, where the resistor is formed on top of gate edge isolation structures, eliminating the need for polysilicon cut etches and recessing, and using the same material layer as the gate structures for self-alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional precision resistors are used in integrated circuit fabrication, then resistance functionality is achieved, but process variations increase and temperature coefficients worsen
Solution Approach 1:
The patent merges the precision resistor formation with the gate structure formation by using the same polysilicon layer for both. The resistor is created within the gate polysilicon layer through selective doping and patterning, eliminating the need for separate resistor fabrication processes. This integration reduces process variations by using a common material layer and simplifies the overall fabrication process.
Solution Approach 2:
The polysilicon layer serves multiple functions: it forms both the gate structures and the precision resistors. By making the polysilicon layer multi-functional, the patent eliminates the need for dedicated resistor material layers and reduces the total number of fabrication steps, thereby improving manufacturing precision and reducing process variations.
2Manufacturing precision
If conventional precision resistors are used, then resistance functionality is achieved, but fabrication complexity and cost increase
Solution Approach 1:
The patent combines precision resistor fabrication with gate structure fabrication into a single integrated process. The same polysilicon layer, doping steps, and patterning processes are used for both gates and resistors, significantly reducing fabrication complexity and eliminating the need for separate resistor processing modules.
Solution Approach 2:
The polysilicon layer is designed to serve dual purposes as both gate material and resistor material. This multi-functionality approach reduces the number of material depositions, patterning steps, and etching processes required, thereby simplifying the overall device fabrication and reducing manufacturing costs.
3Manufacturing precision
If conventional precision resistors are used, then resistance functionality is achieved, but integration with SAGE architecture becomes difficult
Solution Approach 1:
The patent integrates precision resistors directly into the SAGE (Self-Aligned Gate) architecture by forming resistors within the gate polysilicon layer. The selective removal of polysilicon in specific regions creates resistors that are naturally self-aligned with the gate structures, achieving seamless integration without requiring additional alignment steps or modifying the SAGE architecture.
4Manufacturing precision
If additional etching steps are added to create precision resistors, then resistor formation is achieved, but process complexity and time increase
Solution Approach 1:
The patent combines resistor formation with gate formation by using the same polysilicon etching steps for both structures. The selective doping and patterning processes that define gate regions also define resistor regions, eliminating the need for separate resistor etching steps and reducing overall fabrication time while maintaining precision.
Data Source
AI summary
A method for fabricating a semiconductor structure includes forming a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is formed over a first of the plurality of semiconductor fins. A second gate structure is formed over a second of the plurality of semiconductor fins. A gate edge isolation structure is formed laterally between and in contact with the first gate structure and the second gate structure, the gate edge isolation structure on the trench isolation region and extending above an uppermost surface of the first gate structure and the second gate structure. A precision resistor is formed on the gate edge isolation structure, wherein the precision resistor and the first gate structure and second gate structure comprise a same material layer.