Precision Sampling Circuit With Dual-Rail Delay Chain Resolution
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Solution Overview
Problem
Conventional voltage-to-time conversion techniques in integrated circuits suffer from low precision and inefficiency due to the inability to accurately determine power supply voltage, leading to improper operation or unnecessary power consumption when measurements are incorrect.
Innovation Solution
A digital voltage regulator circuit with a dual rail delay chain and cross-coupled inverters that enhance resolution and reduce metastability, allowing for precise power supply voltage determination by using a dual-sided signal domain and simultaneous data and complement signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional voltage-to-time conversion techniques are used, then the circuit can determine power supply voltage, but the measurement precision is insufficient leading to incorrect voltage determination
Solution Approach 1:
The delay chain is segmented into multiple stages with intermediate sampling points, allowing multiple measurements to be taken along the signal path. This segmentation enables more data points to be collected for voltage determination, improving measurement precision and reliability
Solution Approach 2:
The patent transitions from single-rail to dual-rail delay chains, adding a dimensional aspect to the measurement system. By sampling both data and complement signals simultaneously, the system obtains more comprehensive information about the delay characteristics, enhancing voltage measurement accuracy
2Measurement precision
If conventional single-rail delay chains are used, then the device complexity is low, but the resolution and precision of voltage measurement are insufficient
Solution Approach 1:
The patent merges the data and complement delay chains into a unified dual-rail structure with cross-coupled inverters. This integration allows both signals to be processed simultaneously through corresponding stages, improving measurement precision while managing device complexity through systematic design
Solution Approach 2:
The dual-rail delay chain structure serves multiple functions: it provides delay measurement for voltage determination, generates complementary signals simultaneously, and enables cross-coupling for enhanced resolution. This multi-functionality improves precision without proportionally increasing complexity
3Measurement precision
If internal data complement generation is used in flip-flops, then the circuit structure is simple, but metastability occurs reducing sampling precision
Solution Approach 1:
The data complement signal is generated in advance by the dual-rail delay chain before reaching the flip-flop, rather than being generated internally during the sampling process. This preliminary action eliminates metastability issues and improves sampling precision
Solution Approach 2:
The dual-rail delay chain acts as an intermediary that provides both data and complement signals to the flip-flop. This intermediary structure ensures signals are properly synchronized and eliminates the need for complex internal complement generation within the flip-flop itself
4Measurement precision
If fewer data points are sampled in the delay chain, then the device complexity is low, but the measurement precision and operating efficiency are insufficient
Solution Approach 1:
The delay chain is divided into multiple stages with intermediate sampling points, enabling numerous data points to be collected efficiently. This segmentation increases measurement precision while the systematic structure maintains operating efficiency through organized signal processing
Data Source
AI summary
A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input.