Transistor Pre-Clean Protection Layer for SAC Isolation
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Solution Overview
Problem
As processing nodes for transistors shrink, the self-aligned contact (SAC) process leads to reduced electrical isolation and increased likelihood of current leakage and shorting due to protrusions and reduced sidewall spacer thickness, affecting transistor yield.
Innovation Solution
A pre-cleaning technique using a protection layer on capping layers and sidewall spacers to minimize material removal during oxide cleaning, forming a metal silicide layer and conductive contact while maintaining electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a pre-cleaning operation is performed to remove native oxides from source/drain regions, then oxide removal effectiveness is improved, but material removal from capping layers and sidewall spacers increases leading to chopping and clipping
Solution Approach 1:
A protection layer is introduced as an intermediary between the pre-cleaning chemistry and the capping layer/sidewall spacer. This protection layer selectively protects the capping layer and sidewall spacer from material removal while allowing effective oxide removal from the source/drain region, thus resolving the contradiction between cleaning effectiveness and structural integrity
Solution Approach 2:
The protection layer is formed before the pre-cleaning operation to prevent material removal from critical structures. By performing this protective action in advance, the capping layer and sidewall spacer are shielded from chopping and clipping during the subsequent oxide removal process
2Productivity
If processing nodes are shrunk to increase transistor density, then transistor density is improved, but electrical isolation between gates and source/drain regions deteriorates
Solution Approach 1:
The protection layer serves as a mediator that enables aggressive pre-cleaning necessary for scaled devices while preventing damage to the capping layer and sidewall spacer. This allows the process to support smaller processing nodes without compromising electrical isolation
Solution Approach 2:
The introduction of the protection layer changes the chemical selectivity parameters of the pre-cleaning process, allowing differentiation between oxide removal rate and material removal rate from the capping layer, thus enabling better control at scaled dimensions
3Length of moving object
If capping layers are made thinner to reduce contact size, then contact pitch is improved, but susceptibility to chopping and clipping during pre-cleaning increases
Solution Approach 1:
The protection layer acts as a buffer that allows thin capping layers to be used for reduced contact pitch while preventing them from being damaged during pre-cleaning. The protection layer absorbs the chemical attack that would otherwise affect the thin capping layer
Solution Approach 2:
The protection layer provides beforehand cushioning against the harsh pre-cleaning chemistry. By placing this protective barrier in advance, thin capping layers are shielded from material removal that would cause chopping and clipping
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances electrical isolation, reduces current leakage, and increases transistor yield by preventing chopping or clipping of capping layers and sidewall spacers.
Implementation Method 1
the protection layer resists removal of material from the dielectric capping layer during the pre-clean operation
Implementation Method 2
performing a pre-clean operation to remove native oxides from a top surface of a source/drain region
Implementation Method 3
a conductive material is deposited on the source/drain region, and the transistor is subjected to a high-temperature anneal which causes the conductive material to react with silicon of the source/drain region to form the metal silicide layer
Data Source
AI summary
A pre-cleaning technique described herein may be used to remove native oxides and/or other contaminants from a semiconductor device in a manner in which the likelihood of chopping, clipping, and/or sidewall spacer thickness reduction is reduced. As described herein, a protection layer is formed on a capping layer over a gate structure of a transistor. A pre-cleaning operation is then performed to remove native oxides from the top surface of a source/drain region of the transistor. In the pre-cleaning operation, the protection layer is consumed instead of the material of the capping layer. In this way, the use of the protection layer reduces the likelihood of removal of material from the capping layer and/or reduces the amount of material that is removed from the capping layer during the pre-cleaning operation.