Parallel Precoder Circuit for DPSK Timing Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing precoder circuits for differential phase shift keying (DPSK) modulation face challenges in ensuring timing margins, particularly when handling large data volumes, as the number of cascade-connected logic circuits increases, leading to difficulties in processing operations within a single cycle.
Innovation Solution
The proposed precoder circuit employs multiple levels of parallel precoder units that perform precoding operations using multiple symbols and one-symbol preceding modulated signals, synchronized by re-timing units, and offset units that add a phase difference between fixed values and preceding modulated signals, allowing simultaneous parallel processing and phase adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of cascade-connected logic circuits is increased to handle large data volumes, then the data processing capability is improved, but the timing margin is degraded
Solution Approach 1:
The precoder circuit is divided into multiple parallel precoder units (first through fourth units) that process different groups of data signals simultaneously. Each unit handles a subset of the input data, reducing the processing burden on individual logic circuit paths and maintaining timing margins while increasing overall data processing capability.
2Productivity
If parallel processing is implemented to improve processing speed, then the productivity is improved, but the device complexity is increased
Solution Approach 1:
The circuit is segmented into four parallel precoder units, each with identical internal structure but processing different data groups. This modular approach enables parallel processing while maintaining manageable complexity through structural repetition and standardization.
Solution Approach 2:
Delay circuits are introduced as intermediary elements to synchronize the outputs from parallel precoder units. These delay circuits act as mediators that align the timing of processed signals from different parallel paths, enabling coherent combination of results while maintaining the benefits of parallel processing.
Data Source
AI summary
A disclosed precoder circuit is used for differential phase shift keying and includes multiple levels of parallel precoder units, each of which is configured to perform a precoding operation using a data signal having multiple symbols and one of a fixed value and a one-symbol preceding modulated signal output from a preceding-level parallel precoder unit so as to obtain a modulated signal, precoding operations of the parallel precoder units being simultaneously performed in a parallel fashion; multiple levels of re-timing units configured to synchronize modulated signals output from the parallel precoder units; and multiple levels of offset units, each of which is configured to add a phase difference between the fixed value and the one-symbol preceding modulated signal to the modulated signals output from the corresponding re-timing units.