Precompiled Instructions for Semiconductor Hardware Control
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Solution Overview
Problem
Current semiconductor processing systems face challenges in efficiently and flexibly controlling hardware devices due to the lack of deterministic feedback verification and the difficulty in modifying hardcoded solutions, which can lead to processing errors and increased costs.
Innovation Solution
A distributed control system is implemented with an upper-level controller that pre-compiles instructions for lower-level controllers, including interlock checks, allowing for simulation and verification of device operations before execution, ensuring reliable and efficient control of hardware devices with real-time interlock checking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If instructions are hardcoded in lower-level controllers for fast execution, then execution speed is improved, but flexibility and ease of modification deteriorate
Solution Approach 1:
The patent pre-compiles high-level instructions into low-level machine code before execution and loads them into the lower-level controller's memory. This preliminary compilation action enables fast execution (like hardcoded solutions) while maintaining the flexibility of high-level programming languages, as the compiled code can be regenerated when modifications are needed without changing the hardware itself.
2Reliability
If the control system waits for feedback from IOC before issuing next command, then deterministic verification is improved, but processing time increases
Solution Approach 1:
The patent performs interlock checks and feedback verification during the pre-compilation phase before the program is executed. By verifying conditions beforehand and embedding the results in the compiled instruction set, the system eliminates runtime waiting for feedback while maintaining deterministic verification, thus resolving the time-reliability contradiction.
Solution Approach 2:
The patent skips the traditional sequential process of issuing commands and waiting for feedback by pre-verifying all interlock conditions during compilation. The compiled code directly executes verified instructions without runtime delays, effectively rushing through the verification process during compilation rather than during execution.
3Speed
If critical sequence portions are distributed to IOC for direct execution, then execution speed is improved, but ability to verify feedback deteriorates
Solution Approach 1:
The patent introduces an intermediary compilation layer that translates high-level instructions with embedded feedback verification requirements into low-level machine code. This intermediary process ensures that feedback verification logic is preserved in the compiled code, allowing distributed execution at IOC while maintaining the ability to verify feedback through the pre-compiled instruction set.
Data Source
AI summary
Disclosed are apparatus and methods for embodiments for efficiently and flexibly controlling hardware devices in a semiconductor processing system are provided for use in a distributed control arrangement. In general, the distributed arrangement includes at least one upper-level controller that is configurable with a computer program sequence of instructions for controlling one or more hardware devices of a processing tool. The hardware devices are controlled through one or more lower-level controllers. Prior to execution of the program sequence of the upper-level controller, at least one instruction of this program is pre-compiled so as to translate the instruction for execution by a selected lower-level controller and to add an at least one interlock check to such pre-compiled instruction and make the translated instruction accessible to at least one lower-level controller. The interlock check specifies one or more condition(s) for the selected lower-level controller to execute the pre-compiled instruction. Any number of instructions of the upper-level controller may be translated for use by any number of selected lower-level controllers, where some of the translated instructions include one or more interlock checks.