Precomputed Cache Coherence for Shared-Memory Multiprocessors

The patent applies preliminary action by precomputing the coherence protocol before runtime execution. The system analyzes the compute graph and hardware topology in advance to determine which caches will hold which data, pre-generating the coherence protocol that will be needed during execution. This eliminates the need for complex runtime coherence analysis, as the protocol is already established and can be directly implemented during workload execution.

The system performs the coherence analysis action beforehand by examining the compute graph and hardware topology to pre-determine cache allocation and coherence requirements. This preliminary analysis generates a coherence protocol that is then executed without further analysis during runtime, thereby ensuring correct coherence behavior while eliminating the need for resource-consuming processing during actual workload execution.

The patent applies preliminary action by performing the learning-based optimization and task scheduling before runtime. The system uses learning-based approaches to analyze the compute graph and hardware topology, determining optimal task distribution and cache allocation in advance. Once the optimal schedule is computed and the coherence protocol is generated, neither the learning-based analysis nor the optimization computations are needed during execution, thereby achieving resource optimization without incurring computational overhead during runtime.