Pre-conditioning Circuits for Programmable Impedance Memory Elements
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Solution Overview
Problem
Conventional forming steps for programmable impedance elements, such as CBRAM devices, apply the same electrical conditions used for programming and erasing, which can lead to inefficiencies and suboptimal results, particularly in the 'fresh' state before initial programming or erasing.
Innovation Solution
The introduction of pre-conditioning methods that apply distinct electrical conditions, including varying voltages and currents, specifically designed for 'fresh' memory elements, differing from standard programming and erasing operations, to prepare these elements for optimal data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional forming steps apply the same electrical conditions as programming and erasing, then the process is simple and uses existing circuits, but the yield and performance of fresh memory elements are suboptimal
Solution Approach 1:
The patent applies a preliminary forming operation specifically designed for fresh memory elements before normal programming and erasing operations. This forming operation uses distinct electrical conditions (higher voltage, different pulse sequences) tailored to the initial state of fresh elements, optimizing their performance before regular use. This resolves the contradiction by introducing a specialized preliminary step that improves yield without requiring fundamental changes to the overall device structure.
Solution Approach 2:
The patent changes the electrical parameters (voltage levels, pulse durations, current magnitudes) used during the forming operation compared to standard programming and erasing operations. By using higher voltages and specific pulse sequences during forming, the patent optimizes the initial state of memory elements, improving yield while maintaining compatibility with existing circuitry through parameter optimization rather than structural changes.
2Productivity
If conventional forming steps use the same electrical conditions as programming and erasing, then existing circuits can be used, but the process is inefficient and suboptimal for fresh elements
Solution Approach 1:
The forming operation serves as a preliminary action that prepares fresh memory elements for efficient subsequent programming and erasing operations. By applying optimized electrical conditions during forming, the patent reduces the number of ineffective cycles needed and improves overall process efficiency, resolving the contradiction between using existing circuits and achieving optimal performance.
Solution Approach 2:
The patent optimizes energy efficiency by changing electrical parameters during the forming operation to match the specific needs of fresh elements. By using appropriately scaled voltages and pulse sequences, the forming process avoids unnecessary energy consumption while effectively preparing elements for regular operations, thus improving productivity without excessive energy loss.
3Reliability
If fresh memory elements undergo conventional forming steps, then the process is straightforward, but the resistance states and reliability are suboptimal
Solution Approach 1:
The patent improves reliability by changing the electrical parameters during forming to better match the requirements of fresh memory elements. By using higher voltages and optimized pulse sequences, the forming operation achieves more effective resistance state formation in fewer cycles, reducing the time required while improving reliability.
Solution Approach 2:
The forming operation applies localized optimization by tailoring the electrical conditions specifically to the state of fresh memory elements. This localized approach ensures that the forming process is optimized for the initial state of elements, improving reliability without requiring excessive time, as the conditions are specifically adapted to the needs of fresh elements rather than using a one-size-fits-all approach.
Data Source
AI summary
A memory device can include a plurality of programmable impedance elements programmable between a low impedance state in response to a program voltage and a higher impedance state in response to an erase voltage having a different polarity than the program voltage; a programming circuit configured to apply the program and erase voltages to selected elements; and a pre-condition path configured to apply a pre-condition voltage only of the erase voltage polarity to fresh elements in a pre-condition operation; wherein fresh elements are elements that have not been subject to any programming voltages. The pre-condition electrical conditions can also include high voltage low current conditions that apply a greater magnitude voltage and smaller current than the first or second electrical conditions, or high voltage low current conditions that apply a greater magnitude voltage and greater current than the first or second electrical conditions.