Pre-Conversion Rounding Instructions to Prevent Double Rounding
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Solution Overview
Problem
Data processing systems face double rounding errors when converting floating point numbers from one format to another, especially when the mantissa field is reduced in multiple stages, leading to inconsistent results.
Innovation Solution
The introduction of floating point and integer pre-conversion instructions that use round-to-nearest ties to even rounding mode, followed by concatenation with zero suffixes to maintain the correct mantissa field size, preventing double rounding errors by preparing the mantissa field for subsequent reductions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If floating point numbers are converted from one format to another through multiple rounding stages, then the conversion process becomes simpler to implement, but double rounding errors occur leading to incorrect results
Solution Approach 1:
The patent applies preliminary action by performing the rounding operation in advance during the format conversion process, before subsequent mantissa truncation occurs. The decoder circuitry rounds the mantissa field to the target precision and then truncates trailing bits in a single pipeline stage, preventing double rounding errors while maintaining implementation simplicity.
2Device complexity
If the mantissa field is reduced in size through multiple rounding operations, then the data processing becomes more manageable, but the precision of the final result deteriorates due to cumulative rounding errors
Solution Approach 1:
The patent performs the precision-determining rounding operation as a preliminary step in the conversion pipeline, establishing the final mantissa precision before any truncation occurs. This single preliminary rounding operation, followed by bit truncation, maintains precision while making the data processing manageable through systematic pipeline design.
Solution Approach 2:
The patent segments the mantissa field into significant bits and trailing bits, applying rounding to the significant portion and systematically discarding the trailing portion. This segmentation allows precise control over which bits contribute to the final precision and which are discarded, preventing cumulative rounding errors.
3Manufacturing precision
If a single rounding operation is performed directly from initial to final mantissa length, then conversion accuracy is maintained, but the processing complexity increases
Solution Approach 1:
The patent segments the mantissa field into significant bits and trailing bits that will be discarded, allowing the rounding operation to focus only on the significant portion. This segmentation simplifies the processing complexity by clearly defining which bits require rounding and which can be systematically truncated without affecting accuracy.
Solution Approach 2:
The patent performs rounding as a preliminary operation in the conversion pipeline, establishing the final precision before truncation. This preliminary rounding, combined with systematic truncation of trailing bits, maintains conversion accuracy while keeping processing complexity manageable through clear operational sequencing.
4Reliability
If floating point pre-conversion instructions are added to the instruction set, then double rounding errors are prevented, but the device complexity increases
Solution Approach 1:
The patent segments the floating point conversion process into distinct operations: format conversion with rounding, and mantissa truncation. By segmenting the conversion process and providing a dedicated pre-conversion instruction that performs rounding to the target precision, the patent improves reliability while managing device complexity through clear operational separation.
Solution Approach 2:
The patent introduces a pre-conversion instruction that performs preliminary rounding to the target mantissa precision before subsequent truncation operations. This preliminary action ensures accuracy by establishing the correct precision early in the pipeline, while the modular instruction design keeps device complexity manageable.
Data Source
AI summary
Apparatus for processing data includes processing circuitry 16, 18, 20, 22, 24, 26 and decoder circuitry 14 for decoding program instructions. The program instructions decoded include a floating point pre-conversion instruction which performs round-to-nearest ties to even rounding upon the mantissa field of an input floating number to generate an output floating point number with the same mantissa length but with the mantissa rounded to a position corresponding to a shorter mantissa field. The output mantissa field includes a suffix of zero values concatenated the rounded value. The decoder for circuitry 14 is also responsive to an integer pre-conversion instruction to quantise and input integer value using round-to-nearest ties to even rounding to form an output integer operand with a number of significant bits matched to the mantissa size of a floating point number to which the integer is later to be converted using an integer-to-floating point conversion instruction.