Pre-cut Underfill Film on Dicing Tape for Thinned Wafer Integrity

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Solution Overview

Problem

Thinned silicon semiconductor wafers are fragile and require dicing methods that minimize physical stress, while conventional fabrication processes often involve multiple steps that can compromise wafer integrity, particularly due to thermal mismatch issues between semiconductors and substrates during flip chip packaging.

Innovation Solution

A method involving a dicing tape with precut underfill material applied directly to the semiconductor wafer, eliminating a step in the conventional process and facilitating stealth dicing by providing both support and encapsulation in a single step, thereby reducing physical stress during dicing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional multi-step fabrication processes are used to apply underfill material to thinned semiconductor wafers, then underfill encapsulation is achieved, but wafer integrity is compromised due to physical stress and multiple processing steps

Engineering Contradiction:
Improvewafer integrityVSAvoidnumber of fabrication steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the underfill material and dicing tape into a single integrated structure. The underfill material is applied directly onto the dicing tape before wafer bonding, eliminating the need for separate underfill application steps and reducing the total number of fabrication steps while maintaining wafer integrity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The underfill material is pre-applied to the dicing tape before the wafer is bonded to the substrate. This preliminary action ensures that underfill encapsulation is already in place before dicing, protecting the wafer during subsequent processing steps and eliminating the need for separate underfill application after wafer thinning.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If thinned semiconductor wafers undergo multiple processing steps, then fabrication completeness is achieved, but physical stress damages the fragile wafer

Engineering Contradiction:
Improvefabrication completenessVSAvoidwafer strength
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

By merging the underfill material and dicing tape into one integrated component, the patent reduces the number of separate processing steps required. This allows fabrication completeness to be achieved with fewer steps, minimizing cumulative physical stress on the fragile thinned wafer.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The underfill material is preliminarily applied to the dicing tape before wafer processing. This ensures that protective encapsulation is in place before the wafer undergoes any processing steps, protecting wafer strength while still allowing complete fabrication to proceed.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If separate steps are used for underfill application and dicing tape mounting, then process control is improved, but manufacturing efficiency decreases

Engineering Contradiction:
Improveprocess controlVSAvoidmanufacturing efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent merges underfill application and dicing tape mounting into a single integrated step. The underfill material is pre-applied to the dicing tape, so that when the wafer is bonded, both underfill encapsulation and tape support are achieved simultaneously. This eliminates one entire process step, significantly improving manufacturing efficiency while maintaining adequate process control.

Inventive Principle:
Principle #5Merging (Combining)

4Ease of manufacture

If conventional dicing methods are used on thinned wafers, then dicing is completed, but wafer damage occurs due to physical stress

Engineering Contradiction:
Improvedicing completionVSAvoidwafer integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The underfill material is preliminarily applied to the dicing tape before the wafer is bonded and diced. This creates a protective cushion between the wafer and the dicing process, reducing physical stress during dicing and preventing wafer damage while still allowing dicing to be completed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The underfill material serves as a cushioning layer that is in place before the dicing process begins. This beforehand cushioning protects the fragile thinned wafer from physical stress during dicing, maintaining wafer integrity while allowing dicing completion.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the risk of wafer damage and maintains die strength by integrating underfill material and dicing tape in a single step, enhancing the efficiency and integrity of the dicing process for thinned semiconductor wafers.

Implementation Method 1

aligning the underfill material on the dicing support tape with the semiconductor wafer and laminating the underfill material to the semiconductor wafer

Methodology Applied
Scientific EffectLamination: Lamination

Data Source

PatentUS9362105B2Pre-cut wafer applied underfill film on dicing tape
Publication Date: 2016.06.07 HENKEL KGAA
  • US9362105B2 patent drawing
  • US9362105B2 patent drawing
  • US9362105B2 patent drawing

AI summary

A method for preparing a semiconductor with preapplied underfill comprises (a) providing a thinned silicon semiconductor wafer having a plurality of metallic bumps on its active face and, optionally, through-silica-vias vertically through the silicon semiconductor wafer; (b) providing an underfill material on a dicing support tape, in which the underfill material is precut to the shape of the semiconductor wafer; (c) aligning the underfill material on the dicing support tape with the semiconductor wafer and laminating the underfill material to the semiconductor wafer.