Pre-decoding Circuitry for Abnormal Instruction Identification
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Solution Overview
Problem
Existing data processing apparatuses face significant power consumption issues due to decoding instructions after pre-decoding, particularly in systems with multiple instruction sets, as multiple decoders are required, leading to increased power and area costs, especially for handling abnormal instructions which must be decoded deterministically.
Innovation Solution
The solution involves shifting the identification of abnormal instructions to the pre-decode stage by providing an abnormal instruction identifier during the pre-decoding process, using side band bits or converting abnormal instructions into a predetermined undefined format, thereby reducing the need for additional decoding circuitry and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If pre-decoding mechanisms are used to identify abnormal instructions, then the power consumption of later decoder circuits is reduced, but the cache must store instructions in a wider format increasing area usage
Solution Approach 1:
The pre-decoding circuitry performs identification of abnormal instructions, branch instructions, and instruction boundaries before storing instructions in the cache. This preliminary action allows the cache to store pre-decoded instructions with embedded identification information, eliminating the need for complex decoding circuits to perform these identifications later, thereby reducing decoder power consumption while using cache area for storage
2Adaptability or versatility
If multiple separate decoders are provided for multiple instruction sets, then support for multiple instruction sets is achieved, but power consumption increases significantly
Solution Approach 1:
The pre-decoding circuitry is designed to handle multiple instruction sets universally by identifying common features such as abnormal instructions, branch instructions, and instruction boundaries that apply across different instruction sets. This single pre-decoding unit performs functions that would otherwise require multiple separate decoders, reducing power consumption while maintaining multi-instruction set support
3Loss of time
If pre-decoding is performed to improve performance, then instruction decoding time is reduced, but the instruction cache must accommodate wider instruction formats
Solution Approach 1:
The pre-decoding circuitry performs decoding operations in advance before instructions are stored in the cache, embedding identification information for abnormal instructions, branch instructions, and instruction boundaries within the pre-decoded instruction format. This allows the cache to store preprocessed instructions that can be quickly retrieved and executed without repeated decoding, reducing decoding time while using cache area for storage
Data Source
AI summary
The present invention provides a data processing apparatus comprising processing circuitry for executing a sequence of instructions and pre-decoding circuitry for receiving the instructions fetched from memory. The pre-decoding circuitry performs a pre-decoding operation to generate corresponding pre-decoded instructions and stores them in a cache for access by the processing circuitry. For each instruction fetched from the memory, the pre-decoding circuitry detects whether the instruction is an abnormal instruction and upon such detection provides in association with a corresponding pre-decoded instruction an identifier identifying that instruction as abnormal.