Multi-Level Pre-Decoding Circuitry for Cache Power Reduction
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Solution Overview
Problem
Existing data processing systems face challenges in reducing power consumption and improving performance due to the power-intensive nature and performance impact of pre-decoding operations, which are typically performed at a single cache level.
Innovation Solution
A multi-level pre-decoding mechanism is introduced, where pre-decode circuitry is associated with both a unified cache and a further cache, performing initial and further pre-decode operations to generate partially and fully pre-decoded instructions, respectively, thereby reducing processing load and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pre-decoding operations are performed at a single cache level, then instructions can be pre-identified and prepared for execution, but power consumption increases and performance is impacted due to the power-intensive nature of pre-decoding
Solution Approach 1:
The pre-decoding operation is divided into two segments: a first pre-decode operation performed at a first cache level (generating partially pre-decoded instructions) and a second pre-decode operation performed at a second cache level (generating fully pre-decoded instructions). This segmentation allows the system to balance between processing throughput and power consumption by distributing the pre-decoding workload across different cache levels rather than concentrating it at a single level.
2Productivity
If pre-decoding operations are performed to generate additional information for instruction identification, then instruction processing performance is improved, but the processing load and time increase
Solution Approach 1:
The system performs preliminary pre-decoding actions at the first cache level before instructions are transferred to the second cache level. The first pre-decode operation generates partially pre-decoded instructions that contain some identification information in advance, so that when instructions reach the second cache level, further pre-decoding can be completed more efficiently, reducing the overall pre-decoding time critical path.
3Speed
If pre-decode information is stored in cache, then instruction boundaries and branch instructions can be identified faster, but cache space is consumed
Solution Approach 1:
Different cache levels are assigned different qualities of pre-decoded information based on their specific functions. The first cache level stores partially pre-decoded instructions with basic identification information, while the second cache level stores fully pre-decoded instructions with complete identification information. This local quality differentiation allows the system to optimize cache space usage by storing only the necessary amount of pre-decode information at each cache level.
Data Source
AI summary
A hierarchical cache with at least a unified cache is used to store both instructions and data values, and a further cache coupled between processing circuitry and a unified cache. The unified cache has a plurality of cache lines identified as an instruction cache line or a data cache line. Each data cache line stores at least one data value and the associated information. Pre-decode circuitry is associated with the unified cache and performs a first pre-decode operation on a received instruction for that instruction cache line in order to generate a corresponding partially pre-decoded instruction for storing in the instruction cache line. Further pre-decode circuitry is associated with the further cache, and, when a partially pre-decoded instruction is routed to the further cache, performs a further pre-decode operation on the partially pre-decoded instruction to generate a corresponding pre-decoded instruction for storage in the further cache.