Pre-decoded Address Decoding Block for Non-volatile Memory

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Solution Overview

Problem

Non-volatile memory designs face challenges in achieving compact circuitry with greater capacity and lower power consumption, particularly in efficiently decoding address information for memory operations like erase operations across sectors and sub-sectors.

Innovation Solution

The proposed solution involves a decoding block with a latch and voltage shift circuit that preprocesses address information, shifting voltage levels to differentiate logic levels, allowing for efficient selection of memory cells and sectors during operations like erasing, while reducing the number of voltage shift circuits needed and eliminating sector-to-sector p-well separation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If traditional address decoding circuits are used in non-volatile memory, then the memory can perform read, write, and erase operations, but the circuitry occupies large area and consumes excessive power

Engineering Contradiction:

Improvedecoder circuit areaVSAvoidmemory capacity density

Core Design Contradiction:

Area of stationary objectVSProductivity

Solution Approach 1:

The address decoding function is segmented into two stages: a pre-decoder that generates intermediate decoded signals, and a final decoder that uses these signals along with additional address bits to select memory cells. This segmentation allows the main decoder to be smaller since it only needs to decode the difference between addresses rather than the full address space.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The pre-decoder performs preliminary decoding of the most significant address bits before the final decoding stage. By pre-computing decoded signals for the upper address bits and storing them in latches, the system reduces the complexity and area of the final decoder circuit while maintaining full addressing capability.

Inventive Principle:

Principle #10Preliminary action

2Use of energy by stationary object

If traditional address decoding circuits are used in non-volatile memory, then the memory can perform read, write, and erase operations, but the power consumption is excessive

Engineering Contradiction:

Improvedecoder power consumptionVSAvoidmemory capacity density

Core Design Contradiction:

Use of energy by stationary objectVSProductivity

Solution Approach 1:

The decoding function is divided into pre-decoding and final decoding stages, with each stage processing only a portion of the address space. This reduces the number of decode lines active simultaneously, thereby reducing power consumption while maintaining full memory capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The pre-decoder generates and latches intermediate decoded signals in advance, so that during the final decoding stage, only minimal additional switching is required. This reduces the dynamic power consumption of the decoder circuitry during memory operations.

Inventive Principle:

Principle #10Preliminary action

3Measurement precision

If full address decoding is performed for each memory operation, then precise memory cell selection is achieved, but the circuit complexity increases

Engineering Contradiction:

Improvememory cell selection precisionVSAvoiddecoder circuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The address decoding is segmented into multiple stages: the pre-decoder processes the most significant address bits to generate intermediate decoded signals, and the final decoder combines these with the least significant address bits to achieve precise memory cell selection. This segmentation reduces the complexity of each individual decoding stage while maintaining precise addressing capability.

Inventive Principle:

Principle #1Segmentation

4Adaptability or versatility

If memory is organized into sectors and sub-sectors for efficient erase operations, then erase flexibility is improved, but the address decoding circuitry becomes more complex

Engineering Contradiction:

Improveerase operation flexibilityVSAvoidaddress decoding circuit complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory is segmented into sectors and sub-sectors, and the address decoding circuit is segmented to handle sector identification and sub-sector identification separately. The pre-decoder handles sector decoding while the final decoder handles sub-sector selection, allowing flexible erase operations at both sector and sub-sector levels without requiring a single complex decoding circuit.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9275708B2Row address decoding block for non-volatile memories and methods for decoding pre-decoded address information

Publication Date: 2016.03.01 MICRON TECHNOLOGY INC

AI summary

Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage shift circuit configured to receive first pre-decoded address information at first voltage levels and further configured to latch the first pre-decoded address information and shift the voltage levels of the same to second voltage levels. An address decoder includes a second latch and voltage shift circuit configured to receive second pre-decoded address information at the first voltage levels and latch and shift the voltage levels of the same to the second voltage levels. The address decoder is further configured to select control gates of the memory cells of the memory based at least in part on the first and second pre-decoded address information.