Pre-decoded Instruction Consistency Checking Across Cache Line Boundaries

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In data processing systems that pre-decode instructions and store them in a cache, there is a challenge with instructions crossing cache line boundaries, leading to potential inconsistencies and incorrect operation due to cache evictions and re-loading of altered instruction portions.

Innovation Solution

The implementation of checking circuitry that identifies and checks the consistency of pre-decoded instruction portions across cache line boundaries for specific types of instructions, such as arithmetic and load/store operations, to trigger re-generation of the instruction when inconsistencies are detected, thereby ensuring accurate execution without significantly impacting system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If pre-decoded instructions are stored in cache with finite capacity and cache eviction mechanism is implemented, then new pre-decoded instructions can be allocated space in cache, but portions of pre-decoded instructions crossing cache line boundaries may be evicted while other portions remain, leading to inconsistency and incorrect operation

Engineering Contradiction:
Improveinstruction execution throughputVSAvoidinstruction consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by checking whether a pre-decoded instruction crosses a cache line boundary before allowing cache eviction. The checking circuitry identifies instructions that span multiple cache lines and prevents eviction of such instructions, ensuring that the entire instruction remains intact in the cache. This preliminary check avoids the problem of splitting instructions across cache lines, which could lead to inconsistency and incorrect operation.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If consistency checking is performed on all pre-decoded instructions crossing cache line boundaries, then instruction consistency is ensured, but system performance is significantly impacted due to overhead

Engineering Contradiction:
Improveinstruction consistencyVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by performing consistency checking only on specific types of pre-decoded instructions that cross cache line boundaries, rather than all instructions. The checking circuitry is configured to identify and check only certain instruction types, allowing the system to maintain instruction consistency for critical operations while minimizing the overhead impact on overall system performance.

Inventive Principle:
Principle #3Local quality

3Use of energy by moving object

If pre-decoded instructions are stored in cache to reduce energy consumption and simplify decoding, then energy efficiency and decoding speed are improved, but cache evictions may cause portions of instructions to be lost or altered

Engineering Contradiction:
Improvedecoding energy consumptionVSAvoidinstruction integrity
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by checking whether a pre-decoded instruction crosses a cache line boundary before allowing cache eviction. The checking circuitry identifies instructions that span multiple cache lines and prevents eviction of such instructions, ensuring that the entire instruction remains intact in the cache. This preliminary check avoids the problem of splitting instructions across cache lines, which could lead to inconsistency and incorrect operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7925867B2Pre-decode checking for pre-decoded instructions that cross cache line boundaries
Publication Date: 2011.04.12 ARM LTD
  • US7925867B2 patent drawing
  • US7925867B2 patent drawing
  • US7925867B2 patent drawing

AI summary

A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in the cache for access by the processing circuitry. If a pre-decoded instruction crosses a cache line boundary, then checking circuitry in respect of selected types of pre-decoded instruction checks for consistency between the first portion of the pre-decoded instruction stored within a first cache line and a contiguous second portion of the pre-decoded instruction stored within a second cache line. If this consistency check is passed such that the two portions are self-consistent, then the pre-decoded instruction can be further decoded and issued. If the consistency check is failed, or the pre-decoded instruction is not of a type for which consistency checking is supported, then re-generation of the pre-decoded instruction is triggered.