Pre-Decoding Decoder Layout for Compact LCD Source Drivers
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Solution Overview
Problem
Conventional digital-to-analog converters in source drivers for LCDs require a large chip area and high power consumption due to the increasing number of transistors needed for higher resolution, making them costly and inefficient.
Innovation Solution
A compact decoder layout structure with pre-decoding switch arrays is implemented, comprising a main switch array and two pre-decoding switch arrays, arranged in a rectangular layout to reduce the number of transistors and power consumption, allowing for efficient selection of gamma voltages based on digital data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the source driver is increased to support higher color depth, then the display quality is improved, but the chip area and power consumption increase significantly
Solution Approach 1:
The decoder is divided into three separate switch arrays (main switch array and two pre-decoding switch arrays), each handling a portion of the digital data. This segmentation allows the large 10-bit decoding function to be distributed across multiple smaller, more compact units, reducing the overall chip area required while maintaining full resolution capability
Solution Approach 2:
The patent transitions from a conventional single-plane decoder layout to a three-dimensional hierarchical structure with pre-decoding stages. By adding the dimension of hierarchical processing (pre-decoding → main decoding), the patent achieves compact 2D layout while maintaining 10-bit resolution functionality that would otherwise require excessive area in a flat architecture
2Measurement precision
If the number of transistors in the decoder is increased to achieve higher resolution, then the display quality is improved, but the power consumption increases
Solution Approach 1:
The decoder functionality is segmented into three switch arrays that operate in a hierarchical pre-decoding manner. This segmentation enables the system to process 10-bit digital data through multiple smaller decoding stages, reducing the simultaneous switching activity and thereby lowering power consumption compared to a single large decoder operating at full resolution
Solution Approach 2:
The pre-decoding switch arrays perform preliminary decoding of portions of the digital data before the main switch array processes the final output. This preliminary action reduces the complexity and switching requirements of the main decoder, resulting in lower overall power consumption while maintaining full 10-bit resolution capability
3Measurement precision
If a full-type decoder with 1024 transistor rows is used to handle 10-bit digital data, then the decoding accuracy is improved, but the circuit area becomes very large
Solution Approach 1:
The full-type decoder is segmented into three smaller switch arrays (main switch array and two pre-decoding switch arrays) that collectively handle 10-bit digital data. Each array manages a subset of the decoding function, reducing the area required for each individual array while maintaining the overall 1024-level decoding accuracy through their hierarchical combination
Solution Approach 2:
The patent adds a hierarchical dimension to the decoder architecture by introducing pre-decoding stages. This transforms the conventional single-plane 1024-row decoder into a multi-layer structure where pre-decoding arrays process intermediate results, achieving the same decoding accuracy with a compact 2D layout that fits within practical chip area constraints
Data Source
AI summary
Provided is a decoder for receiving a digital data and outputting an analog voltage. The decoder comprising a main switch array, a first pre-decoding switch array, and a second pre-decoding switch array. The main switch array receives the digital data and outputs a voltage if the digital data is in a first range. The first pre-decoding switch array is for receiving the digital data, pre-decoding a part of the digital data, and outputting a voltage if the digital data is in a second range. The second pre-decoding switch array is for receiving the digital data, pre-decoding the part of the digital data, and outputting a voltage if the digital data is in a third range. Combination of the main switch array, the first pre-decoding switch array, and the second pre-decoding switch array is in a substantially rectangular layout structure.