Pre-defined Via Patterns for IC Package Yield
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Solution Overview
Problem
The increasing complexity and miniaturization of electronic devices pose challenges in IC packaging, including constrained routing density, high manufacturing costs, and increased complexity due to the need for additional redistribution layers and higher I/O per device, which complicates the fabrication process and increases the risk of faulty via connections.
Innovation Solution
The method involves pre-defining via locations and patterns on a substrate before coupling an electronic device, allowing for inspection and exclusion of defective via patterns, thereby ensuring functional connections and reducing manufacturing costs by preventing faulty vias from being coupled to electronic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional redistribution layers are added to create desired double-sided I/O systems, then the I/O capability is improved, but the number of processing steps increases, further increasing the cost and complexity of the manufacturing process
Solution Approach 1:
The patent pre-defines via locations and patterns on the substrate before coupling the electronic device. This preliminary action allows via patterns to be inspected and defective ones excluded before the actual device coupling, thereby simplifying the manufacturing process by preventing faulty connections early in the production flow rather than requiring complex rework or additional redistribution layers later.
2Ease of manufacture
If via locations are defined after coupling the electronic device, then the manufacturing process is simpler, but defective via connections cannot be detected until after coupling, increasing the risk of inoperable devices
Solution Approach 1:
The patent defines via locations and patterns on the substrate in advance, before coupling the electronic device. This preliminary definition enables inspection and exclusion of defective via patterns prior to device coupling, maintaining manufacturing simplicity while significantly improving via connection reliability by preventing faulty connections from being made.
Solution Approach 2:
The patent implements a feedback mechanism where via patterns are inspected after being pre-defined on the substrate. Defective via patterns are identified and excluded based on this inspection feedback before the electronic device is coupled, ensuring that only functional via connections proceed to the next manufacturing stage.
3Reliability
If the substrate is removed after via formation, then the via connections are cleaner and more reliable, but the substrate provides structural support during manufacturing that must be maintained
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: first forming via connections with the substrate in place to maintain structural support, then selectively removing portions of the substrate to expose and clean the via connections. This segmentation allows both structural integrity during manufacturing and connection quality after formation to be optimized separately.
Data Source
AI summary
An electronic package is provided. The electronic package includes a substrate and a plurality of vias defined by a corresponding plurality of pre-defined via patterns. The electronic package further a metal built-up layer disposed on portions of the substrate to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias. Also, the electronic package includes a first conductive layer disposed on at least a portion of the metal built-up layer. Moreover, the electronic package includes a second conductive layer disposed on the first conductive layer, where the plurality of vias is disposed at least in part in the metal built-up layer, the first conductive layer, and the second conductive layer.