Predicate Logic Circuitry for VLIW Processor Pipeline Stall Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In Very Long Instruction Word (VLIW) processor architectures, there is a dependency between compare and branch operations that leads to pipeline stalls, which existing technologies fail to adequately address due to limited branch prediction and increased power consumption.

Innovation Solution

A processor with multiple parallel execution pipelines that executes compare and dependent instructions concurrently, using predicate logic circuitry to provide the compare result early to the branch instruction, allowing for simultaneous execution and reducing dependency-related latencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If compare and branch instructions are executed sequentially with traditional dependency handling, then the branch instruction can correctly depend on the compare result, but pipeline stalls occur reducing processor productivity

Engineering Contradiction:
Improvecorrect dependency handlingVSAvoidprocessor throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The processor is divided into multiple independent execution pipelines (first execution pipeline for compare instruction, second execution pipeline for branch instruction) that can operate simultaneously. This segmentation allows the compare and branch instructions to be executed in parallel without traditional sequential dependency, resolving the contradiction between reliable dependency handling and processor throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Predicate logic circuitry acts as an intermediary between the first execution pipeline (compare) and the second execution pipeline (branch). The predicate logic receives the compare result and selectively controls the commitment of the branch instruction result, enabling correct dependency handling while maintaining parallel execution and preventing pipeline stalls.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If branch prediction techniques are used to eliminate branch dependencies, then processor productivity improves, but device complexity and power consumption increase

Engineering Contradiction:
Improvebranch execution efficiencyVSAvoidprocessor architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the dependency resolution function from complex branch prediction logic and implements it instead through simple predicate logic circuitry. By taking out the need for sophisticated branch prediction hardware and replacing it with straightforward predicate-based control, the solution improves productivity while avoiding increased device complexity and power consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If compare result is made available early to dependent instructions, then pipeline stalls are reduced improving productivity, but the risk of committing incorrect results increases

Engineering Contradiction:
Improveinstruction execution speedVSAvoidresult commitment accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The predicate logic circuitry provides feedback control by monitoring the compare result and selectively enabling or disabling the commitment of the branch instruction result. This feedback mechanism ensures that even when the compare result is made available early to the second execution pipeline, only correct results are committed, preventing reliability issues while maintaining high productivity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8990543B2System and method for generating and using predicates within a single instruction packet
Publication Date: 2015.03.24 QUALCOMM INC
  • US8990543B2 patent drawing
  • US8990543B2 patent drawing
  • US8990543B2 patent drawing

AI summary

In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.