Predicated Loop Memory Burst Transfers in High-Level Synthesis
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Solution Overview
Problem
Conventional Electronic Design Automation (EDA) tools are limited in their ability to recognize opportunities for implementing burst transfer mode in high-level synthesis, particularly in loop constructs with conditional statements, leading to suboptimal hardware performance.
Innovation Solution
A system and method for analyzing loop structures in high-level synthesis to identify sequential memory accesses and transform them into burst transfers by generating an intermediate representation, detecting loop predicates, and inserting intrinsics to facilitate burst transfer mode in integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional EDA tools are used for high-level synthesis, then the design can be implemented in integrated circuit, but the ability to recognize burst transfer opportunities is limited resulting in suboptimal hardware performance
Solution Approach 1:
The patent segments the analysis process into distinct phases: generating intermediate representation from high-level code, analyzing loop structures separately, detecting predicate information in conditional statements, and identifying sequential memory access patterns. This segmentation allows the tool to systematically recognize burst transfer opportunities that conventional tools miss, thereby improving data throughput without overwhelming complexity
Solution Approach 2:
The patent introduces an intermediate representation (IR) as a mediator between the high-level programming language and the hardware description language. This IR serves as a bridge that preserves semantic information about loop structures and memory access patterns, enabling the EDA tool to detect burst transfer opportunities while maintaining design fidelity. The IR acts as an intermediary layer that conventional tools skip, thus resolving the contradiction between ease of implementation and detection capability
2Speed
If burst transfer mode is implemented for sequential memory accesses, then data transfer speed improves significantly, but the complexity of the EDA tool increases
Solution Approach 1:
The patent performs preliminary analysis of loop structures and predicate information during the intermediate representation phase, before generating the final hardware description. By pre-identifying sequential memory access patterns and burst transfer opportunities in the IR, the tool can automatically insert appropriate burst transfer instructions without requiring complex real-time analysis during synthesis, thus improving data transfer speed while managing tool complexity through advance preparation
Solution Approach 2:
The patent transforms the representation of memory access operations by changing parameters in the intermediate representation. It modifies how memory accesses are described by adding metadata about sequential patterns, access strides, and predicate conditions. This parameter transformation enables the EDA tool to recognize burst transfer opportunities using structured data rather than complex pattern matching, thereby achieving high data transfer speeds with controlled tool complexity
3Productivity
If conventional memory access handling is used in loop bodies with conditional statements, then the implementation is simpler, but the throughput is reduced due to inability to aggregate sequential accesses
Solution Approach 1:
The patent segments the loop body analysis by identifying basic blocks and separating conditional statements from sequential memory accesses. It analyzes predicate information in conditional statements independently while tracking memory access patterns in sequential blocks. This segmentation enables the tool to aggregate sequential accesses for burst transfer without being overwhelmed by the complexity of nested conditionals, thereby improving throughput with manageable analysis complexity
Solution Approach 2:
The patent extracts predicate information from conditional statements within loop bodies and separates it from the memory access analysis. By taking out the predicate logic and analyzing it independently, the tool can focus on identifying sequential memory access patterns without being constrained by the conditional structure complexity. This extraction enables effective throughput improvement while keeping the analysis mechanism relatively simple
Data Source
AI summary
Implementing burst transfers for predicated accesses in high-level synthesis includes generating, using computer hardware, an intermediate representation of a design specified in a high-level programming language. The design is for an integrated circuit. Using the computer hardware, loop predicate information for one or more conditional statements within a loop body of the intermediate representation is determined. A plurality of memory accesses of the loop body guarded by the one or more conditional statements are determined to be sequential memory accesses based on the predicate information. The intermediate representation is modified by inserting one or more intrinsics therein indicating that the sequential memory accesses are to be implemented using a burst transfer mode of the integrated circuit.