Predicated Multiply-Accumulate Circuitry for Flexible Filter Operations
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Solution Overview
Problem
Existing MAC circuitry lacks flexibility and efficiency in performing variable sequences of multiply-add and multiply-subtract operations, particularly in filter operations, due to the need for precompiled sequences and inefficient use of memory and resources.
Innovation Solution
A predicated multiply-accumulate instruction is introduced, allowing data processing circuitry to perform either multiply-add or multiply-subtract operations based on a predicate value, enabling flexible operation selection at runtime and reducing memory requirements by storing magnitude in a single scalar register.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dedicated MAC unit is used to perform filter operations with variable sequences of multiply-add and multiply-subtract operations, then operational flexibility and efficiency are improved, but traditional approaches require precompiled sequences and high memory usage which worsen adaptability and code density
Solution Approach 1:
The patent introduces a dynamic predicate value that can be changed at runtime to control whether multiply-add or multiply-subtract operations are performed. This allows the MAC unit to adapt to different operation sequences without requiring precompiled instruction sequences, resolving the contradiction between maintaining high throughput and achieving operational flexibility.
Solution Approach 2:
The patent changes the parameter of the MAC operation by introducing a predicate value that determines the operation type (add or subtract). This single parameter change allows the same hardware to perform different operations dynamically, improving adaptability without sacrificing productivity.
2Adaptability or versatility
If pilot signal information is encoded as large vectors in memory to enable filter operations, then operational flexibility is improved, but memory space requirements and code density worsen
Solution Approach 1:
The patent extracts the critical information from large pilot signal vectors and stores only the essential predicate values in memory. This extraction approach maintains the ability to handle different pilot signals while dramatically reducing memory requirements, as only small predicate values need to be stored rather than complete signal vectors.
Solution Approach 2:
The patent uses scalar registers to store predicate values that can be replicated and used across multiple MAC operations. This copying mechanism allows the same predicate information to control multiple operations without requiring redundant storage, improving code density while maintaining adaptability.
3Measurement precision
If separate multiply-add and multiply-subtract instructions are used to perform filter operations, then operational precision is improved, but instruction sequence complexity and code density worsen
Solution Approach 1:
The patent merges the multiply-add and multiply-subtract operations into a single unified MAC instruction that is controlled by a predicate value. This consolidation maintains operational precision while dramatically simplifying the instruction sequence, as only one instruction type needs to be implemented and executed rather than separate instructions for each operation type.
Solution Approach 2:
The patent creates a universal MAC instruction that can perform both multiply-add and multiply-subtract operations through the use of a predicate value. This multi-functional instruction reduces code density requirements and simplifies the instruction set while maintaining the precision of both operation types.
Data Source
AI summary
A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques.