Predicated Warp Post-Synchronization for Divergent Thread Performance

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Solution Overview

Problem

Current SIMT architectures face performance degradation due to costly synchronization operations that occur before instruction execution, especially when dealing with divergent threads.

Innovation Solution

A method for synchronizing divergent threads by receiving instructions with set-synchronization and predicated synchronization commands, monitoring active threads, and updating masks to enable synchronization only after instruction execution, allowing for predication of synchronization commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If synchronization commands are appended to instructions before execution, then thread synchronization is achieved, but processing performance decreases due to costly pre-execution synchronization operations

Engineering Contradiction:
Improvethread synchronizationVSAvoidprocessing performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary actions by pushing synchronization tokens onto stacks before instruction execution, but the actual synchronization operation is delayed until after instruction completion. This allows the system to prepare synchronization metadata in advance while executing instructions without being blocked by pre-execution synchronization costs.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where the graphics processor monitors active masks and synchronization tokens to determine when threads have completed their instructions. This feedback loop enables the system to perform synchronization only when necessary, after instruction execution, rather than forcing pre-execution synchronization that degrades performance.

Inventive Principle:
Principle #23Feedback

2Reliability

If all threads are synchronized before instruction execution, then thread safety is ensured, but unnecessary synchronization operations increase processing costs

Engineering Contradiction:
Improvethread safetyVSAvoidprocessing costs
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by differentiating between active and inactive threads through active masks. Instead of synchronizing all threads uniformly, the system performs synchronization only for active threads that have divergent execution paths, thereby reducing unnecessary synchronization operations and associated processing costs.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements partial action by performing synchronization only for the subset of threads that actually diverged and require resynchronization, rather than synchronizing all threads in the warp. This partial synchronization approach reduces processing costs while maintaining thread safety for the necessary threads.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If synchronization is performed before instruction execution, then thread coordination is achieved, but instruction execution efficiency is reduced

Engineering Contradiction:
Improvethread coordinationVSAvoidinstruction execution efficiency
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent performs preliminary actions by preparing synchronization tokens and active masks before instruction execution, but the actual synchronization blocking is delayed until after instruction completion. This separation of preparation and execution allows instructions to run at full speed without being blocked by pre-execution synchronization, while still achieving thread coordination.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent inverts the traditional synchronization timing by performing synchronization after instruction execution rather than before. This inversion allows instructions to execute efficiently without pre-blocking, while thread coordination is achieved through post-execution synchronization that waits for all threads to complete their instructions first.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS8850436B2Opcode-specified predicatable warp post-synchronization
Publication Date: 2014.09.30 NVIDIA CORP
  • US8850436B2 patent drawing
  • US8850436B2 patent drawing
  • US8850436B2 patent drawing

AI summary

One embodiment of the present invention sets forth a technique for performing a method for synchronizing divergent executing threads. The method includes receiving a plurality of instructions that includes at least one set-synchronization instruction and at least one instruction that includes a synchronization command, and determining an active mask that indicates which threads in a plurality of threads are active and which threads in the plurality of threads are disabled. For each instruction included in the plurality of instructions, the instruction is transmitted to each of the active threads included in the plurality of threads. If the instruction is a set-synchronization instruction, then a synchronization token, the active mask and the synchronization point is each pushed onto a stack. Or, if the instruction is a predicated instruction that includes a synchronization command, then each active thread that executes the predicated instruction is monitored to determine when the active mask has been updated to indicate that each active thread, after executing the predicated instruction, has been disabled.