Predicting Semiconductor Lithography Overlay Yield via Via Attribute Measurement
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Solution Overview
Problem
Advanced packaging processes in semiconductor manufacturing face challenges in achieving high yield due to alignment errors and defects in redistribution layers (RDLs) and vias, which can lead to cascading issues affecting subsequent layers and overall package performance.
Innovation Solution
A method is introduced to predict the overlay yield of semiconductor lithography processes by measuring attributes of conductive vias before lithography, comparing them to predefined values, and using this data to adjust alignment or scrap batches, while also virtually modeling layers to identify potential defects and their impact on subsequent layers, allowing for informed decision-making on continuing fabrication or scrapping substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional electronic packaging processes are used, then manufacturing simplicity is maintained, but alignment precision and yield are insufficient for advanced packaging requirements
Solution Approach 1:
The patent measures and evaluates via attributes (position, diameter, depth) before conducting lithography processes. This preliminary assessment allows prediction of overlay yield and identification of potential alignment issues before they affect subsequent layers, enabling proactive correction rather than reactive troubleshooting.
Solution Approach 2:
The patent creates a virtual model of the semiconductor substrate that replicates the physical substrate's via attributes and layer structure. This digital twin allows simulation of lithography processes and defect propagation without consuming physical materials, enabling virtual optimization of alignment parameters before actual fabrication.
2Reliability
If lithography processes are conducted without prior via measurement, then productivity is maintained, but overlay yield prediction accuracy deteriorates
Solution Approach 1:
The system performs via attribute measurements and overlay yield predictions before lithography processes. By assessing via quality in advance, the system can identify substrates requiring rework or adjustment, preventing wasted lithography cycles on defective substrates and improving overall process efficiency.
Solution Approach 2:
The patent replaces physical trial-and-error lithography processes with virtual modeling and prediction. The virtual substrate model simulates lithography outcomes based on measured via attributes, allowing prediction of overlay yield without conducting actual lithography experiments on physical substrates.
3Reliability
If defects are detected early in the fabrication process, then yield optimization improves, but inspection time and resource expenditure increase
Solution Approach 1:
The system performs via attribute measurements at the beginning of the fabrication process, before subsequent lithography and packaging steps. This early detection allows identification of substrates with potential defects that would propagate through later layers, enabling targeted inspection and intervention.
Solution Approach 2:
The virtual substrate model replicates the physical substrate's via attributes and layer structure, allowing simulation of defect propagation through multiple layers. This digital twin enables prediction of how early defects will affect subsequent lithography layers and overall package yield without requiring physical inspection of each layer.
4Measurement precision
If virtual modeling of substrate layers is performed, then defect prediction accuracy improves, but computational complexity and processing time increase
Solution Approach 1:
The patent creates a virtual model that replicates the physical substrate's via attributes (position, diameter, depth) and layer structure. This digital twin allows simulation of lithography processes and defect propagation through multiple layers, enabling accurate prediction of overlay yield and potential failures without physical experimentation.
Solution Approach 2:
The virtual modeling process performs defect prediction and overlay yield assessment before actual lithography processes. By simulating potential defects and their propagation in the virtual model, the system identifies high-risk areas that require closer inspection or process adjustment.
Data Source
AI summary
Tracking and/or predicting the yield of a semiconductor process. In an embodiment, a tracking method monitors the yield at each layer of the process. This can be used to determine how to proceed. In an embodiment, the prediction method measures the values of at least one attribute of each conductive via on a substrate before the lithography process. The measured values are then compared to predefined values for the same attribute, to determine any deviation. Based on this comparison, an overlay yield of the lithography process is predicted.