Prediction Circuitry for Fine-Grained Processor Core Switching
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Solution Overview
Problem
Existing data processing systems with multiple execution mechanisms, like big.LITTLE processors, face limitations in switching granularity, restricting the benefit of energy efficiency due to the need to transfer entire processor state between cores, which is inefficient for fine-grained workload changes between high performance and low power requirements.
Innovation Solution
Incorporating prediction circuitry to predict the next sequence of program instructions and determine the appropriate execution target based on the most recently executed sequence, allowing for more precise switching between high-performance and low-power execution circuitry, using hash values and performance data to optimize execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the entire processor state is transferred between processor cores during switching, then the switching can be performed between high-performance and low-power cores, but the switching granularity becomes too coarse and the switching time becomes excessively long (hundreds of thousands of cycles)
Solution Approach 1:
The invention segments the processor state into two parts: a shared architectural state (registers, program counter, condition codes) that is maintained in a unified location accessible by both high-performance and low-power cores, and a private execution state (instruction pointer, pipeline registers) that is core-specific. This segmentation allows switching between cores without transferring the entire processor state, enabling fine-grained switching with minimal latency.
Solution Approach 2:
The invention introduces a shared state storage mechanism (unified register file or state buffer) that acts as an intermediary between the high-performance core and low-power core. This intermediary allows both cores to access the same architectural state without requiring full state transfer during switching, thereby reducing switching time while maintaining adaptability.
2Adaptability or versatility
If the entire processor state is transferred between processor cores during switching, then switching between execution mechanisms is enabled, but the energy consumption increases due to the large amount of data movement
Solution Approach 1:
By segmenting the processor state into shared architectural state and private execution state, the invention eliminates the need to transfer large amounts of data during core switching. Only minimal context information needs to be updated, significantly reducing energy consumption while preserving the ability to switch between high-performance and low-power execution mechanisms.
Solution Approach 2:
The invention extracts the essential architectural state (registers, program counter, condition codes) from the core-specific execution state and places it in a shared storage location. This extraction allows the low-power core to access the same architectural state without requiring full state transfer, thereby reducing energy consumption while maintaining execution mechanism flexibility.
3Device complexity
If simple prediction based on the most recently executed sequence is used, then the prediction circuitry complexity is reduced, but the prediction accuracy decreases when workload requirements change frequently
Solution Approach 1:
The prediction circuitry dynamically adapts its behavior based on workload characteristics. When workload requirements change frequently, the predictor automatically adjusts by giving more weight to recent execution patterns and less weight to historical data. This dynamic adaptation allows the simple prediction circuitry to maintain high accuracy in changing conditions without increasing complexity.
Solution Approach 2:
The invention implements feedback mechanisms where the actual execution outcomes are used to update and refine the prediction tables. The prediction circuitry continuously learns from past predictions and corrections, improving accuracy over time. This feedback-driven approach enables simple circuitry to achieve high prediction accuracy by adapting to changing workload patterns.
Data Source
AI summary
An apparatus for processing data includes first execution circuitry, such as an out-of-order processor, and second execution circuitry, such as an in-order processor. The first execution circuitry is of higher performance but uses more energy than the second execution circuitry. Control circuitry switches between the first execution circuitry being active and the second execution circuitry being active. The control circuitry includes prediction circuitry which is configured to predict a predicted identity of a next sequence of program instructions to be executed in dependence upon a most recently executed sequence of program instructions and then in dependence upon this predicted identity to predict a predicted execution target corresponding to whether the next sequence of program instructions should be executed by the first execution circuitry or the second execution circuitry.