Processor Prediction State Clearing During Continuous Instruction Execution

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Solution Overview

Problem

Modern processors face performance limitations due to branch prediction mispredictions, which incur power consumption and performance loss, and are susceptible to side-channel security vulnerabilities through their prediction state being leaked or manipulated.

Innovation Solution

A method to sequentially clear subsets of prediction state, such as branch prediction state, upon context or mode switches to protect against side-channel attacks, allowing continued processor operation during clearing, reducing the risk of state leakage and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the prediction state is cleared to protect against side-channel attacks, then security is improved, but processor operation must be stopped which reduces performance

Engineering Contradiction:
ImprovesecurityVSAvoidprocessor performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The prediction state is divided into multiple subsets that can be cleared sequentially rather than all at once. This segmentation allows the clearing operation to be performed in stages, enabling processor operation to continue during the transition between subsets, thereby maintaining security while minimizing performance impact.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The prediction state subsets are cleared in advance of when they would be needed, allowing the clearing operation to be completed before security threats arise. This preliminary action enables security hardening to be performed proactively without interrupting normal processor operations that depend on prediction state.

Inventive Principle:
Principle #10Preliminary action

2Speed

If branch prediction is used to improve performance, then processor speed is improved, but power consumption increases due to mispredictions

Engineering Contradiction:
Improveprocessor speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

Instead of clearing the entire prediction state, only specific subsets are cleared when and where needed. This partial action approach maintains the beneficial prediction state for performance-critical paths while removing only the portions that pose security risks, thereby preserving processor speed while reducing unnecessary power consumption from full state clearing operations.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If the entire prediction state is cleared at once, then security is improved, but processor operation is halted which reduces productivity

Engineering Contradiction:
ImprovesecurityVSAvoidprocessor downtime
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The prediction state clearing operation is segmented into multiple sequential subsets rather than a single monolithic operation. This allows the processor to continue operating during the transitions between subsets, significantly reducing the total downtime while still achieving complete security hardening of the prediction state.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The processor maintains continuous operation during the prediction state clearing process by switching between different subsets of prediction state. This continuity ensures that processor productivity is preserved while the security hardening operation completes in the background without halting useful computational work.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20260064427A1Sequentially clearing subsets of prediction state of processors while continuing to process instructions
Publication Date: 2026.03.05 INTEL CORP
  • US20260064427A1 patent drawing
  • US20260064427A1 patent drawing
  • US20260064427A1 patent drawing

AI summary

A method of an aspect includes processing instructions with a processor, making predictions associated with some of the instructions based on prediction state, clearing a plurality of subsets of the prediction state sequentially, and continuing the processing of the instructions while the plurality of the subsets of the prediction state are being cleared. Other methods, processors, and systems are also disclosed.