Predictive Boosting for 3D NAND Program Disturb
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Solution Overview
Problem
Three-dimensional NAND flash memory devices face challenges in maintaining reliability and speed due to program disturb errors, which increase as the wordline height increases, requiring adaptive boosting methods to prevent data errors without compromising programming performance.
Innovation Solution
The method involves predictive boosting by issuing a program command to a block of memory, assigning an initial bit line bias, and determining the wordline threshold. For wordlines above this threshold, the bit line bias is increased, and precharge time is extended to prevent program disturb errors, with the bias and time adjustments tailored to specific error counts and memory cell positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform bit line bias is applied to all wordlines, then the programming operation is simple, but program disturb errors increase in higher wordlines
Solution Approach 1:
The patent divides the wordline range into two regions: lower wordlines (0 to threshold-1) use an initial bit line bias, while upper wordlines (threshold to max) use a boosted bit line bias. This local differentiation addresses the program disturb issue in higher wordlines without applying complexity uniformly across all wordlines.
Solution Approach 2:
The patent changes the bit line bias parameter from a uniform value to a stepped value, where the bias increases from the initial level to a boosted level at the wordline threshold. This parameter change enables better reliability in upper wordlines while maintaining simplicity in lower wordlines.
2Reliability
If a boosted bit line bias is applied to all wordlines, then program disturb errors are reduced, but programming time increases
Solution Approach 1:
The patent applies the boosted bit line bias only to upper wordlines (threshold to max) where program disturb is problematic, while lower wordlines (0 to threshold-1) continue to use the initial bias. This localized approach reduces overall programming time compared to applying boosted bias universally.
Solution Approach 2:
The patent segments the programming operation into two phases: programming lower wordlines with initial bias, then programming upper wordlines with boosted bias. This segmentation optimizes the balance between reliability and speed by applying enhanced parameters only where necessary.
3Reliability
If the wordline threshold is set low, then more wordlines benefit from boosted bias and program disturb is reduced, but programming speed decreases
Solution Approach 1:
The patent makes the wordline threshold a dynamic parameter that can be adjusted based on detected program disturb conditions. The threshold is determined by monitoring cell states and adjusting the split point between initial and boosted bias regions, optimizing the balance between reliability and throughput for different operating conditions.
Data Source
AI summary
Non-volatile, high performance memory devices balance speed and reliability, which can include channel boosting to reduce data error rates in the memory cells. Vertical NAND strings exhibit greater program disturb (errors) the higher the wordline is on the string. The present disclosure applies a boosted bit line voltage or an increased precharge time when the programming reaches a level (wordline number) where it has been determined that errors due to program disturb may be an issue. The boost to the bit line may occur after a stored wordline value or based on a calculated number of errors at a previous wordline. In an example, the bit line stays the same as the prior world line programming operation until the likely program disturb is determined.